Searched refs:PTE (Results 1 – 25 of 27) sorted by relevance
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194 ; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address215 bnz.d 2f ; YES: PGD == PMD has THP PTE: stop pgd walk221 ; Get the PTE entry: The idea is235 ld.aw r0, [r1, r0] ; r0: PTE (lower word only for PAE40)236 ; r1: PTE ptr243 ; Convert Linux PTE entry into TLB entry244 ; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu245 ; (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])246 ; IN: r0 = PTE, r1 = ptr to PTE254 and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE[all …]
13 access to the table. At the moment we use split lock for PTE and PMD19 maps pte and takes PTE table lock, returns pointer to the taken22 unlocks and unmaps PTE table;24 allocates PTE table if needed and take the lock, returns pointer27 returns pointer to PTE table lock;33 Split page table lock for PTE tables is enabled compile-time if37 Split page table lock for PMD tables is enabled, if it's enabled for PTE57 There's no need in special enabling of PTE split page table lock:59 which must be called on PTE table allocation / freeing.97 The spinlock_t allocated in pgtable_page_ctor() for PTE table and in
18 PTE for this purpose. PTE flags are scarce resource especially on some CPU
130 - map/unmap of the pages with PTE entry increment/decrement ->_mapcount153 File pages get PG_double_map set on first map of the page with PTE and
141 advantage is that PAE has more PTE bits and can provide advanced features
86 During a page fault on a PTE that is a swap entry, frontswap calls the zswap
456 We handle this by keeping PTE-mapped huge pages on normal LRU lists: the457 PMD on border of VM_LOCKED VMA will be split into PTE table.
70 #define pmd_populate_kernel(MM, PMD, PTE) pmd_set(MM, PMD, PTE) argument71 #define pmd_populate(MM, PMD, PTE) pmd_set(MM, PMD, PTE) argument
59 #define pmd_populate_kernel(MM, PMD, PTE) pmd_set(PMD, PTE) argument
7 The soft-dirty is a bit on a PTE which helps to track which pages a task20 64-bit qword is the soft-dirty one. If set, the respective PTE was27 the soft-dirty bit on the respective PTE.33 bits on the PTE.38 the same place. When unmap is called, the kernel internally clears PTE values
111 more page flag is introduced, the Young flag. When the PTE Accessed bit is113 is set on the page. The reclaimer treats the Young flag as an extra PTE
129 a PTE. To make sure the flag is up-to-date one has to read
157 page (via kvm_mmu_notifier_clear_flush_young), it marks the PTE as not-present158 by clearing the RWX bits in the PTE and storing the original R & X bits in160 PTE (using the ignored bit 62). When the VM tries to access the page later on,162 to atomically restore the PTE to a Present state. The W bit is not saved when163 the PTE is marked for access tracking and during restoration to the Present
55 Purpose: Support MMU operations such as writing to PTE,
39 } PTE; typedef
47 table entry (PTE) has the Present bit cleared or other reserved bits set,48 then speculative execution ignores the invalid PTE and loads the referenced50 by the address bits in the PTE was still present and accessible.72 PTE which is marked non present. This allows a malicious user space75 encoded in the address bits of the PTE, thus making attacks more78 The Linux kernel contains a mitigation for this attack vector, PTE92 PTE inversion mitigation for L1TF, to attack physical host memory.132 'Mitigation: PTE Inversion' The host protection is active136 information is appended to the 'Mitigation: PTE Inversion' part:578 - PTE inversion to protect against malicious user space. This is done
8 This check can spot missing TLB invalidation/wrong PTE permissions/
105 DMAR:[fault reason 05] PTE Write access is not set107 DMAR:[fault reason 05] PTE Write access is not set
112 #error PTE shared bit mismatch117 #error Invalid Linux PTE bit settings
73 .long do_page_fault !PTE not present
82 mov %g3, %o2 ! PTE125 mov %g3, %o2 ! PTE
53 userspace page tables to manage. One PTE to lock, one set of
2 * Copyright 2015 Sutajio Ko-Usagi PTE LTD
201 kosagi Sutajio Ko-Usagi PTE Ltd.
51 also save system registers, and hardware PTE's.
