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Searched refs:PP_ASSERT_WITH_CODE (Results 1 – 25 of 28) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/
Dvega12_smumgr.c46 PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT, in vega12_copy_table_from_smc()
48 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega12_copy_table_from_smc()
50 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega12_copy_table_from_smc()
52 PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, in vega12_copy_table_from_smc()
56 PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, in vega12_copy_table_from_smc()
61 PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, in vega12_copy_table_from_smc()
84 PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT, in vega12_copy_table_to_smc()
86 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega12_copy_table_to_smc()
88 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega12_copy_table_to_smc()
94 PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, in vega12_copy_table_to_smc()
[all …]
Dsmu7_smumgr.c40 PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL); in smu7_set_smc_sram_address()
41 …PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINV… in smu7_set_smc_sram_address()
57 …PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return … in smu7_copy_bytes_from_smc()
58 …PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM… in smu7_copy_bytes_from_smc()
94 …PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return … in smu7_copy_bytes_to_smc()
95 …PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM… in smu7_copy_bytes_to_smc()
433 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, in smu7_request_smu_load_fw()
436 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, in smu7_request_smu_load_fw()
439 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, in smu7_request_smu_load_fw()
442 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, in smu7_request_smu_load_fw()
[all …]
Diceland_smumgr.c163 …PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINV… in iceland_upload_smc_firmware_data()
177 PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL); in iceland_upload_smc_firmware_data()
345 PP_ASSERT_WITH_CODE(false, in iceland_populate_dw8()
396 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in iceland_populate_bapm_vddc_vid_sidd()
398 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, in iceland_populate_bapm_vddc_vid_sidd()
400 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in iceland_populate_bapm_vddc_vid_sidd()
409 PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL); in iceland_populate_bapm_vddc_vid_sidd()
422 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8, in iceland_populate_vddc_vid()
446 PP_ASSERT_WITH_CODE(false, in iceland_populate_pm_fuses()
452 PP_ASSERT_WITH_CODE(false, in iceland_populate_pm_fuses()
[all …]
Dvegam_smumgr.c140 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); in vegam_start_smu_in_protection_mode()
212 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); in vegam_start_smu()
795 PP_ASSERT_WITH_CODE((clock >= min), in vegam_get_sleep_divider_id_from_clock()
825 PP_ASSERT_WITH_CODE((0 == result), in vegam_populate_single_graphic_level()
916 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt), in vegam_populate_all_graphic_levels()
966 PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr, in vegam_calculate_mclk_params()
993 PP_ASSERT_WITH_CODE(!result, in vegam_populate_single_memory_level()
999 PP_ASSERT_WITH_CODE(!result, in vegam_populate_single_memory_level()
1047 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1098 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, in vegam_populate_mvdd_value()
[all …]
Dfiji_smumgr.c151 PP_ASSERT_WITH_CODE(false, in fiji_start_smu_in_protection_mode()
230 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, in fiji_setup_graphics_level_structure()
245 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr, in fiji_setup_graphics_level_structure()
253 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr, in fiji_setup_graphics_level_structure()
266 PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr), in fiji_avfs_event_mgr()
270 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr), in fiji_avfs_event_mgr()
274 PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr), in fiji_avfs_event_mgr()
519 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255, in fiji_populate_bapm_parameters_in_dpm_table()
625 PP_ASSERT_WITH_CODE(false, in fiji_populate_dw8()
712 PP_ASSERT_WITH_CODE(false, in fiji_populate_pm_fuses()
[all …]
Dpolaris10_smumgr.c129 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, in polaris10_setup_graphics_level_structure()
140 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address, in polaris10_setup_graphics_level_structure()
147 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, in polaris10_setup_graphics_level_structure()
155 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, in polaris10_setup_graphics_level_structure()
164 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, in polaris10_setup_graphics_level_structure()
180 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr), in polaris10_avfs_event_mgr()
186 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr), in polaris10_avfs_event_mgr()
191 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr), in polaris10_avfs_event_mgr()
237 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); in polaris10_start_smu_in_protection_mode()
307 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); in polaris10_start_smu()
[all …]
Dtonga_smumgr.c442 PP_ASSERT_WITH_CODE(!result, in tonga_populate_smc_voltage_tables()
447 PP_ASSERT_WITH_CODE(!result, in tonga_populate_smc_voltage_tables()
452 PP_ASSERT_WITH_CODE(!result, in tonga_populate_smc_voltage_tables()
457 PP_ASSERT_WITH_CODE(!result, in tonga_populate_smc_voltage_tables()
462 PP_ASSERT_WITH_CODE(!result, in tonga_populate_smc_voltage_tables()
546 PP_ASSERT_WITH_CODE(result == 0, in tonga_calculate_sclk_params()
628 PP_ASSERT_WITH_CODE((!result), in tonga_populate_single_graphic_level()
726 PP_ASSERT_WITH_CODE((pcie_entry_count >= 1), in tonga_populate_all_graphic_levels()
802 PP_ASSERT_WITH_CODE( in tonga_calculate_mclk_params()
977 PP_ASSERT_WITH_CODE( in tonga_populate_single_memory_level()
[all …]
Dvega10_smumgr.c41 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, in vega10_copy_table_from_smc()
43 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega10_copy_table_from_smc()
45 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega10_copy_table_from_smc()
68 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, in vega10_copy_table_to_smc()
70 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega10_copy_table_to_smc()
72 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega10_copy_table_to_smc()
137 PP_ASSERT_WITH_CODE(!smu9_send_msg_to_smc(hwmgr, in vega10_verify_smc_interface()
316 PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr), in vega10_start_smu()
Dci_smumgr.c312 PP_ASSERT_WITH_CODE(result == 0, in ci_calculate_sclk_params()
549 PP_ASSERT_WITH_CODE(false, in ci_populate_dw8()
582 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in ci_populate_bapm_vddc_vid_sidd()
584 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, in ci_populate_bapm_vddc_vid_sidd()
586 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in ci_populate_bapm_vddc_vid_sidd()
610 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8, in ci_populate_vddc_vid()
770 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in ci_get_std_voltage_value_sidd()
850 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL); in ci_populate_smc_vddc_table()
880 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL); in ci_populate_smc_vdd_ci_table()
908 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL); in ci_populate_smc_mvdd_table()
[all …]
Dsmu10_smumgr.c121 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, in smu10_copy_table_from_smc()
123 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in smu10_copy_table_from_smc()
125 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in smu10_copy_table_from_smc()
149 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, in smu10_copy_table_to_smc()
151 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in smu10_copy_table_to_smc()
153 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in smu10_copy_table_to_smc()
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega12_hwmgr.c446 PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr), in vega12_setup_asic_task()
476 PP_ASSERT_WITH_CODE(!ret, in vega12_get_number_of_dpm_level()
481 PP_ASSERT_WITH_CODE(*num_of_levels > 0, in vega12_get_number_of_dpm_level()
497 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, in vega12_get_dpm_frequency_by_index()
514 PP_ASSERT_WITH_CODE(!ret, in vega12_setup_single_dpm_table()
522 PP_ASSERT_WITH_CODE(!ret, in vega12_setup_single_dpm_table()
554 PP_ASSERT_WITH_CODE(!ret, in vega12_setup_default_dpm_tables()
567 PP_ASSERT_WITH_CODE(!ret, in vega12_setup_default_dpm_tables()
580 PP_ASSERT_WITH_CODE(!ret, in vega12_setup_default_dpm_tables()
593 PP_ASSERT_WITH_CODE(!ret, in vega12_setup_default_dpm_tables()
[all …]
Dprocess_pptables_v1_0.c57 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE16____), in set_platform_caps()
59 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE64____), in set_platform_caps()
61 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE512____), in set_platform_caps()
63 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE1024____), in set_platform_caps()
65 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE2048____), in set_platform_caps()
165 PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries), in get_vddc_lookup_table()
325 PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count), in get_valid_clk()
355 PP_ASSERT_WITH_CODE((0 != limitable->ucNumEntries), "Invalid PowerPlay Table!", return -1); in get_hard_limits()
378 PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries), in get_mclk_voltage_dependency_table()
425 PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries), in get_sclk_voltage_dependency_table()
[all …]
Dvega10_hwmgr.c78 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), in cast_phw_vega10_power_state()
88 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), in cast_const_phw_vega10_power_state()
496 PP_ASSERT_WITH_CODE(lookup_table->count != 0, in vega10_get_socclk_for_voltage_evv()
507 PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count, in vega10_get_socclk_for_voltage_evv()
551 PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, in vega10_get_evv_voltages()
558 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), in vega10_get_evv_voltages()
689 PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count, in vega10_sort_lookup_table()
749 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table, in vega10_set_private_data_based_on_pptable()
751 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, in vega10_set_private_data_based_on_pptable()
754 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, in vega10_set_private_data_based_on_pptable()
[all …]
Dsmu7_hwmgr.c113 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), in cast_phw_smu7_power_state()
123 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), in cast_const_phw_smu7_power_state()
164 PP_ASSERT_WITH_CODE((7 >= link_width), in smu7_get_current_pcie_lane_number()
225 PP_ASSERT_WITH_CODE((NULL != voltage_table), in phm_get_svi2_voltage_table_v0()
260 PP_ASSERT_WITH_CODE((0 == result), in smu7_construct_voltage_tables()
271 PP_ASSERT_WITH_CODE((0 == result), in smu7_construct_voltage_tables()
280 PP_ASSERT_WITH_CODE((0 == result), in smu7_construct_voltage_tables()
290 PP_ASSERT_WITH_CODE((0 == result), in smu7_construct_voltage_tables()
299 PP_ASSERT_WITH_CODE((0 == result), in smu7_construct_voltage_tables()
308 PP_ASSERT_WITH_CODE((0 == result), in smu7_construct_voltage_tables()
[all …]
Dvega12_processpptables.c68 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >= in check_powerplay_tables()
71 PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0, in check_powerplay_tables()
150 PP_ASSERT_WITH_CODE( in append_vbios_pptable()
308 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), in vega12_pp_tables_initialize()
312 PP_ASSERT_WITH_CODE((powerplay_table != NULL), in vega12_pp_tables_initialize()
316 PP_ASSERT_WITH_CODE((result == 0), in vega12_pp_tables_initialize()
321 PP_ASSERT_WITH_CODE((result == 0), in vega12_pp_tables_initialize()
325 PP_ASSERT_WITH_CODE((result == 0), in vega12_pp_tables_initialize()
403 PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
413 PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
[all …]
Dvega10_processpptables.c74 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >= in check_powerplay_tables()
77 PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset, in check_powerplay_tables()
79 PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0, in check_powerplay_tables()
81 PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0, in check_powerplay_tables()
130 PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0), in init_thermal_controller()
168 PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8), in init_thermal_controller()
282 PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0), in get_mm_clock_voltage_table()
508 PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries, in get_socclk_voltage_dependency_table()
542 PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries, in get_mclk_voltage_dependency_table()
583 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), in get_gfxclk_voltage_dependency_table()
[all …]
Dsmu_helper.c163 PP_ASSERT_WITH_CODE((NULL != vol_table), in phm_trim_voltage_table()
206 PP_ASSERT_WITH_CODE((0 != dep_table->count), in phm_get_svi2_mvdd_voltage_table()
209 PP_ASSERT_WITH_CODE((NULL != vol_table), in phm_get_svi2_mvdd_voltage_table()
222 PP_ASSERT_WITH_CODE((0 == result), in phm_get_svi2_mvdd_voltage_table()
234 PP_ASSERT_WITH_CODE((0 != dep_table->count), in phm_get_svi2_vddci_voltage_table()
237 PP_ASSERT_WITH_CODE((NULL != vol_table), in phm_get_svi2_vddci_voltage_table()
250 PP_ASSERT_WITH_CODE((0 == result), in phm_get_svi2_vddci_voltage_table()
261 PP_ASSERT_WITH_CODE((0 != lookup_table->count), in phm_get_svi2_vdd_voltage_table()
264 PP_ASSERT_WITH_CODE((NULL != vol_table), in phm_get_svi2_vdd_voltage_table()
347 PP_ASSERT_WITH_CODE((NULL != lookup_table), in phm_get_voltage_index()
[all …]
Dvega12_thermal.c34 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, in vega12_get_current_rpm()
75 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features( in vega12_enable_fan_control_feature()
93 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features( in vega12_disable_fan_control_feature()
110 PP_ASSERT_WITH_CODE( in vega12_fan_ctrl_start_smc_fan_control()
124 PP_ASSERT_WITH_CODE(!vega12_disable_fan_control_feature(hwmgr), in vega12_fan_ctrl_stop_smc_fan_control()
Dvega10_powertune.c802 …PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config … in vega10_program_didt_config_registers()
1185 …PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", re… in vega10_disable_se_edc_force_stall_config()
1202 …PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return re… in vega10_enable_didt_config()
1206 …PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return re… in vega10_enable_didt_config()
1210 …PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return re… in vega10_enable_didt_config()
1216 …PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return re… in vega10_enable_didt_config()
1220 …PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return re… in vega10_enable_didt_config()
1229 …PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", re… in vega10_enable_didt_config()
1249 …PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return … in vega10_disable_didt_config()
1253 …PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return … in vega10_disable_didt_config()
[all …]
Dsmu7_powertune.c902 PP_ASSERT_WITH_CODE((config_regs != NULL), "Invalid config register table.", return -EINVAL); in smu7_program_pt_config_registers()
982 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
984 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
987 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
992 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
995 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
997 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
1000 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
1002 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); in smu7_enable_didt_config()
1008 PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", goto error); in smu7_enable_didt_config()
[all …]
Dvega10_thermal.c187 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( in vega10_enable_fan_control_feature()
204 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( in vega10_disable_fan_control_feature()
221 PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr), in vega10_fan_ctrl_start_smc_fan_control()
237 PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr), in vega10_fan_ctrl_stop_smc_fan_control()
433 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_thermal_enable_alert()
464 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, in vega10_thermal_disable_alert()
Dppatomfwctrl.c64 PP_ASSERT_WITH_CODE(table_address, in pp_atomfwctrl_get_voltage_info_table()
85 PP_ASSERT_WITH_CODE(voltage_info, in pp_atomfwctrl_is_voltage_controlled_by_gpio_v4()
106 PP_ASSERT_WITH_CODE(voltage_info, in pp_atomfwctrl_get_voltage_table_v4()
118 PP_ASSERT_WITH_CODE( in pp_atomfwctrl_get_voltage_table_v4()
154 PP_ASSERT_WITH_CODE(false, in pp_atomfwctrl_get_voltage_table_v4()
171 PP_ASSERT_WITH_CODE(table_address, in pp_atomfwctrl_get_gpio_lookup_table()
217 PP_ASSERT_WITH_CODE(gpio_lookup_table, in pp_atomfwctrl_get_pp_assign_pin()
Dhardwaremanager.c366 PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL); in phm_get_clock_info()
367 PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL); in phm_get_clock_info()
371 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result); in phm_get_clock_info()
382 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result); in phm_get_clock_info()
Dprocesspptables.c856 PP_ASSERT_WITH_CODE(NULL != powerplay_tab, in pp_tables_get_response_times()
1605 PP_ASSERT_WITH_CODE((result == 0), in pp_tables_initialize()
1611 PP_ASSERT_WITH_CODE((result == 0), in pp_tables_initialize()
1616 PP_ASSERT_WITH_CODE((result == 0), in pp_tables_initialize()
1621 PP_ASSERT_WITH_CODE((result == 0), in pp_tables_initialize()
1627 PP_ASSERT_WITH_CODE((result == 0), in pp_tables_initialize()
1632 PP_ASSERT_WITH_CODE((result == 0), in pp_tables_initialize()
1637 PP_ASSERT_WITH_CODE((result == 0), in pp_tables_initialize()
/Linux-v4.19/drivers/gpu/drm/amd/powerplay/inc/
Dpp_debug.h37 #define PP_ASSERT_WITH_CODE(cond, msg, code) \ macro

12