Searched refs:PPLL_REF_DIV (Results 1 – 5 of 5) sorted by relevance
626 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) { in radeon_probe_pll_params()650 m = (INPLL(PPLL_REF_DIV) & 0x3ff); in radeon_probe_pll_params()692 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; in radeon_probe_pll_params()771 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in radeon_get_pllinfo()1352 save->ppll_ref_div = INPLL(PPLL_REF_DIV); in radeon_save_state()1371 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()1410 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()1413 OUTPLLP(PPLL_REF_DIV, in radeon_write_pll_regs()1418 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()1425 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) in radeon_write_pll_regs()[all …]
591 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); in aty_pll_readupdate()616 aty_st_pll(PPLL_REF_DIV, in aty_pll_writeupdate()617 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); in aty_pll_writeupdate()982 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in aty128_timings()991 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); in aty128_timings()1347 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); in aty128_set_pll()
2452 tmp = INPLL(PPLL_REF_DIV);2454 OUTPLL(PPLL_REF_DIV, tmp);2455 INPLL(PPLL_REF_DIV);
244 #define PPLL_REF_DIV 0x0003 macro
431 #define PPLL_REF_DIV 0x0003 macro
