Searched refs:PORT_BASE (Results 1 – 8 of 8) sorted by relevance
117 #define PORT_BASE (0x800) macro119 #define PHY_CFG (PORT_BASE + 0x0)124 #define PROG_PHY_LINK_RATE (PORT_BASE + 0xc)131 #define PHY_CTRL (PORT_BASE + 0x14)134 #define PHY_RATE_NEGO (PORT_BASE + 0x30)135 #define PHY_PCN (PORT_BASE + 0x44)136 #define SL_TOUT_CFG (PORT_BASE + 0x8c)137 #define SL_CONTROL (PORT_BASE + 0x94)140 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)141 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)[all …]
116 #define PORT_BASE (0x2000) macro117 #define PHY_CFG (PORT_BASE + 0x0)118 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)125 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)126 #define PHY_CTRL (PORT_BASE + 0x14)129 #define SL_CFG (PORT_BASE + 0x84)130 #define SL_CONTROL (PORT_BASE + 0x94)135 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)138 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)139 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)[all …]
175 #define PORT_BASE (0x2000) macro177 #define PHY_CFG (PORT_BASE + 0x0)178 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)183 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)186 #define PHY_CTRL (PORT_BASE + 0x14)189 #define SAS_PHY_CTRL (PORT_BASE + 0x20)190 #define SL_CFG (PORT_BASE + 0x84)191 #define PHY_PCN (PORT_BASE + 0x44)192 #define SL_TOUT_CFG (PORT_BASE + 0x8c)193 #define SL_CONTROL (PORT_BASE + 0x94)[all …]
367 typeflags, PORT_BASE, PORT_BASE + port_off); in test_datapath()382 pair_udp_open(fds_udp[0], PORT_BASE); in test_datapath()383 pair_udp_open(fds_udp[1], PORT_BASE + port_off); in test_datapath()
35 #define PORT_BASE 8000 macro
243 pair_udp_open(udp_sock, PORT_BASE); in walk_v1_v2_rx()604 pair_udp_open(udp_sock, PORT_BASE); in walk_v3_rx()
80 #define PORT_BASE 0x100 macro193 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); in ahci_ceva_setup()
58 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) macro59 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
