Home
last modified time | relevance | path

Searched refs:PIPE_B (Results 1 – 25 of 25) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/i915/gvt/
Dhandlers.c756 [PIPE_B] = PRIMARY_B_FLIP_DONE, in pri_surf_mmio_write()
777 [PIPE_B] = SPRITE_B_FLIP_DONE, in spr_surf_mmio_write()
1913 MMIO_D(PIPEDSL(PIPE_B), D_ALL); in init_generic_mmio_info()
1918 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1923 MMIO_D(PIPESTAT(PIPE_B), D_ALL); in init_generic_mmio_info()
1928 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); in init_generic_mmio_info()
1933 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); in init_generic_mmio_info()
1938 MMIO_D(CURCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
1942 MMIO_D(CURPOS(PIPE_B), D_ALL); in init_generic_mmio_info()
1946 MMIO_D(CURBASE(PIPE_B), D_ALL); in init_generic_mmio_info()
[all …]
Ddisplay.c49 pipe = PIPE_B; in get_edp_pipe()
393 [PIPE_B] = PIPE_B_VBLANK, in emulate_vblank_on_pipe()
Dcmd_parser.c1175 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1177 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1233 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
1247 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
Dinterrupt.c450 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
/Linux-v4.19/drivers/gpu/drm/i915/
Di915_reg.h7691 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7694 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7697 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7700 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7719 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7722 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7725 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7728 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7744 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7747 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
[all …]
Dintel_device_info.c749 info->num_scalers[PIPE_B] = 2; in intel_device_info_runtime_init()
769 info->num_sprites[PIPE_B] = 2; in intel_device_info_runtime_init()
816 disabled_mask |= BIT(PIPE_B); in intel_device_info_runtime_init()
824 case BIT(PIPE_B): in intel_device_info_runtime_init()
825 case BIT(PIPE_A) | BIT(PIPE_B): in intel_device_info_runtime_init()
Dintel_dpio_phy.c795 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
807 if (pipe != PIPE_B) { in chv_phy_pre_pll_enable()
828 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
837 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
850 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
960 if (pipe != PIPE_B) { in chv_phy_post_pll_disable()
Dintel_runtime_pm.c842 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
843 i830_enable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_enable()
849 i830_disable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_disable()
857 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
1180 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1310 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
2153 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2320 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2380 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2435 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
[all …]
Dintel_pm.c489 case PIPE_B: in vlv_get_fifo_size()
939 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
940 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
946 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
989 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
990 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in vlv_write_wm_values()
1001 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
1002 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
1014 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
1015 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
[all …]
Dintel_pipe_crc.c175 case PIPE_B: in vlv_pipe_crc_ctl_reg()
274 case PIPE_B: in vlv_undo_pipe_scramble_reset()
Dvlv_dsi.c1053 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
1077 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1695 if (connector->encoder->crtc_mask == BIT(PIPE_B)) in intel_dsi_get_panel_orientation()
1791 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); in vlv_dsi_init()
1795 intel_encoder->crtc_mask = BIT(PIPE_B); in vlv_dsi_init()
Dintel_display.h32 PIPE_B, enumerator
Di915_trace.h89 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
Di915_irq.c761 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
1908 case PIPE_B: in i9xx_pipestat_irq_ack()
2345 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); in ibx_irq_handler()
4356 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
4534 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
4657 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
Dintel_sprite.c567 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_update_plane()
1607 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
Dintel_dp.c597 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
726 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
3054 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
3662 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { in intel_dp_link_down()
6116 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
6119 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
Dintel_display.c1341 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
1359 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_hdmi_disabled()
1479 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1487 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()
1576 I915_WRITE(DPLL(PIPE_B), in i9xx_disable_pll()
1577 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
4568 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); in cpt_set_fdi_bc_bifurcation()
4587 case PIPE_B: in ivybridge_update_fdi_bc_bifurcation()
6004 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in valleyview_crtc_enable()
6403 case PIPE_B: in ironlake_check_fdi_lanes()
[all …]
Dintel_panel.c499 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in _vlv_get_backlight()
1631 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_setup_backlight()
Di915_cmd_parser.c617 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
Dintel_ddi.c1779 case PIPE_B: in intel_ddi_enable_transcoder_func()
1954 *pipe = PIPE_B; in intel_ddi_get_hw_state()
Dintel_drv.h1226 case PIPE_B: in vlv_pipe_to_channel()
Dintel_hdmi.c1413 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { in intel_disable_hdmi()
Dintel_sdvo.c1556 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { in intel_disable_sdvo()
/Linux-v4.19/drivers/video/fbdev/intelfb/
Dintelfbhw.h183 #define PIPE_B 1 macro
Dintelfbhw.c1059 if (pipe == PIPE_B) { in intelfbhw_mode_to_hw()
1302 if (dinfo->pipe == PIPE_B) { in intelfbhw_program_mode()