Searched refs:PIPESRC (Results 1 – 4 of 4) sorted by relevance
269 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> in intel_vgpu_decode_primary_plane()272 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & in intel_vgpu_decode_primary_plane()
2036 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); in init_generic_mmio_info()2046 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); in init_generic_mmio_info()2056 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); in init_generic_mmio_info()
3847 I915_WRITE(PIPESRC(crtc->pipe), in intel_update_pipe_config()7340 I915_WRITE(PIPESRC(pipe), in intel_set_pipe_src_size()7387 tmp = I915_READ(PIPESRC(crtc->pipe)); in intel_get_pipe_src_size()7773 val = I915_READ(PIPESRC(pipe)); in i9xx_get_initial_plane_config()15312 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); in i830_enable_pipe()16107 error->pipe[i].source = I915_READ(PIPESRC(i)); in intel_display_capture_error_state()
4093 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) macro
