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Searched refs:PINMUX_CFG_REG_VAR (Results 1 – 18 of 18) sorted by relevance

/Linux-v4.19/drivers/pinctrl/sh-pfc/
Dpfc-r8a77470.c1689 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
1716 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
1743 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
1770 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
1798 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
1825 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
1852 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
1879 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
1906 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
1933 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
[all …]
Dpfc-sh7734.c1828 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1865 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1900 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1936 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1973 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
2008 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2048 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2092 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2128 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2164 { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
[all …]
Dpfc-emev2.c1594 { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1612 { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1624 { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1636 { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1661 { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1680 { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
Dpfc-r8a7791.c5709 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5768 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5804 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5840 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5878 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5920 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5958 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5998 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
6039 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6082 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7790.c4962 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4998 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5035 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5064 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5097 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5130 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5167 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5203 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5238 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5279 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7778.c2286 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2341 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2384 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2436 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2478 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2520 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2564 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2615 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2654 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2694 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dpfc-r8a7779.c3273 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3311 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3349 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3395 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3446 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3494 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3540 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3577 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3613 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3656 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dpfc-r8a7794.c4860 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4914 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4954 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4989 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5029 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5064 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5099 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5145 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5182 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5217 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7792.c2401 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2459 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2517 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2565 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2611 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2652 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2692 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2734 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
Dsh_pfc.h131 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ macro
629 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
Dpfc-r8a77995.c2406 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2438 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Dpfc-r8a77965.c4493 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4518 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4545 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a7795-es1.c5160 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5187 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5214 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a77990.c2429 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2457 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Dpfc-r8a7796.c5494 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5519 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5546 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a7795.c5551 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5576 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5603 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a77970.c2356 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Dpfc-r8a77980.c2753 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,