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Searched refs:PIC32_CLR (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/drivers/tty/serial/
Dpic32_uart.c81 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), in pic32_uart_set_mctrl()
147 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_stop_tx()
171 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_stop_rx()
187 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_break_ctl()
225 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_do_rx()
382 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_dsbl_and_mask()
384 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), in pic32_uart_dsbl_and_mask()
481 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_startup()
485 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), in pic32_uart_startup()
546 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), in pic32_uart_set_termios()
[all …]
/Linux-v4.19/drivers/irqchip/
Dirq-pic32-evic.c72 writel(BIT(bit), evic_base + PIC32_CLR(REG_INTCON)); in pic32_set_ext_polarity()
118 evic_base + PIC32_CLR(REG_IPC_OFFSET + reg * 0x10)); in pic32_set_irq_priority()
156 iecclr = PIC32_CLR(REG_IEC_OFFSET + reg * 0x10); in pic32_irq_domain_map()
157 ifsclr = PIC32_CLR(REG_IFS_OFFSET + reg * 0x10); in pic32_irq_domain_map()
262 u32 ifsclr = PIC32_CLR(REG_IFS_OFFSET + (i * 0x10)); in pic32_of_init()
/Linux-v4.19/drivers/rtc/
Drtc-pic32.c115 PIC32_CLR(PIC32_RTCALRM))); in pic32_rtc_setaie()
131 writel(PIC32_RTCALRM_AMASK, base + PIC32_CLR(PIC32_RTCALRM)); in pic32_rtc_setfreq()
298 writel(PIC32_RTCCON_ON, base + PIC32_CLR(PIC32_RTCCON)); in pic32_rtc_enable()
303 writel(3 << 9, base + PIC32_CLR(PIC32_RTCCON)); in pic32_rtc_enable()
/Linux-v4.19/arch/mips/include/asm/mach-pic32/
Dpic32.h22 #define PIC32_CLR(_reg) ((_reg) + 0x04) macro
/Linux-v4.19/drivers/watchdog/
Dpic32-dmt.c59 writel(DMT_ON, PIC32_CLR(dmt->regs + DMTCON_REG)); in dmt_disable()
123 writel(RESETCON_DMT_TIMEOUT, PIC32_CLR(rst_base)); in pic32_dmt_bootstatus()
Dpic32-wdt.c72 writel(RESETCON_WDT_TIMEOUT, PIC32_CLR(wdt->rst_base)); in pic32_wdt_bootstatus()
125 writel(WDTCON_ON, PIC32_CLR(wdt->regs + WDTCON_REG)); in pic32_wdt_stop()
/Linux-v4.19/arch/mips/pic32/pic32mzda/
Dconfig.c120 writel(-1, PIC32_CLR(pic32_conf_base + PIC32_RCON)); in pic32_config_init()
/Linux-v4.19/drivers/clk/microchip/
Dclk-core.c123 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
273 writel(REFO_ON | REFO_OE, PIC32_CLR(refo->ctrl_reg)); in roclk_disable()
535 writel(REFO_ON, PIC32_CLR(refo->ctrl_reg)); in roclk_set_rate_and_parent()
985 writel(sosc->enable_mask, PIC32_CLR(sosc->enable_reg)); in sosc_clk_disable()
/Linux-v4.19/drivers/pinctrl/
Dpinctrl-pic32.c1816 writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); in pic32_gpio_request_enable()
1848 writel(mask, bank->reg_base + PIC32_CLR(PORT_REG)); in pic32_gpio_set()
1858 writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG)); in pic32_gpio_direction_output()
1956 writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); in pic32_pinconf_set()
2015 writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG)); in pic32_gpio_irq_mask()
2045 writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG)); in pic32_gpio_irq_set_type()
2051 writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG)); in pic32_gpio_irq_set_type()