Searched refs:PHY (Results 1 – 25 of 406) sorted by relevance
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| /Linux-v4.19/Documentation/ |
| D | phy.txt | 2 PHY subsystem
7 This document explains the Generic PHY Framework along with the APIs provided,
13 *PHY* is the abbreviation for physical layer. It is used to connect a device
14 to the physical medium e.g., the USB controller has a PHY to provide functions
17 controllers have PHY functionality embedded into it and others use an external
18 PHY. Other peripherals that use PHY include Wireless LAN, Ethernet,
21 The intention of creating this framework is to bring the PHY drivers spread
25 This framework will be of use only to devices that use external PHY (PHY
28 Registering/Unregistering the PHY provider
31 PHY provider refers to an entity that implements one or more PHY instances.
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| /Linux-v4.19/drivers/phy/ti/ |
| D | Kconfig | 5 tristate "TI DA8xx USB PHY Driver"
10 Enable this to support the USB PHY on DA8xx SoCs.
12 This driver controls both the USB 1.1 PHY and the USB 2.0 PHY.
15 tristate "TI dm816x USB PHY driver"
24 tristate "OMAP CONTROL PHY Driver"
27 Enable this to add support for the PHY part present in the control
28 module. This driver has API to power on the USB2 PHY and to write to
30 power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
31 additional register to power on USB3 PHY/SATA PHY/PCIE PHY
32 (PIPE3 PHY).
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| /Linux-v4.19/drivers/phy/broadcom/ |
| D | Kconfig | 5 tristate "Broadcom Cygnus PCIe PHY driver"
10 Enable this to support the Broadcom Cygnus PCIe PHY.
14 tristate "Broadcom Kona USB2 PHY Driver"
18 Enable this to support the Broadcom Kona USB 2.0 PHY.
21 tristate "Broadcom Northstar USB 2.0 PHY Driver"
26 Enable this to support Broadcom USB 2.0 PHY connected to the USB
30 tristate "Broadcom Northstar USB 3.0 PHY Driver"
36 Enable this to support Broadcom USB 3.0 PHY connected to the USB
40 tristate "Broadcom Northstar2 PCIe PHY driver"
45 Enable this to support the Broadcom Northstar2 PCIe PHY.
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| /Linux-v4.19/drivers/phy/qualcomm/ |
| D | Kconfig | 5 tristate "Atheros AR71XX/9XXX USB PHY driver"
11 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
14 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
21 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
28 tristate "Qualcomm QMP PHY Driver"
32 Enable this to support the QMP PHY transceiver that is used
36 tristate "Qualcomm QUSB2 PHY Driver"
41 Enable this to support the HighSpeed QUSB2 PHY transceiver for USB
43 PHY which is usually paired with either the ChipIdea or Synopsys DWC3
47 tristate "Qualcomm UFS PHY driver"
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| /Linux-v4.19/drivers/phy/rockchip/ |
| D | Kconfig | 5 tristate "Rockchip Display Port PHY Driver"
9 Enable this to support the Rockchip Display Port PHY.
12 tristate "Rockchip EMMC PHY Driver"
16 Enable this to support the Rockchip EMMC PHY.
27 Support for Rockchip USB2.0 PHY with Innosilicon IP block.
30 tristate "Rockchip PCIe PHY Driver"
36 Enable this to support the Rockchip PCIe PHY.
39 tristate "Rockchip TYPEC PHY Driver"
45 Enable this to support the Rockchip USB TYPEC PHY.
48 tristate "Rockchip USB2 PHY Driver"
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| /Linux-v4.19/drivers/phy/ |
| D | Kconfig | 2 # PHY
5 menu "PHY Subsystem"
8 bool "PHY Core"
10 Generic PHY support.
12 This framework is designed to provide a generic interface for PHY
14 API by which phy drivers can create PHY using the phy framework and
15 phy users can obtain reference to the PHY. All the users of this
19 tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver"
24 Enable this to support NXP LPC18xx/43xx internal USB OTG PHY.
30 tristate "IMG Pistachio USB2.0 PHY driver"
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| /Linux-v4.19/Documentation/devicetree/bindings/phy/ |
| D | phy-bindings.txt | 2 information about PHY subsystem refer to Documentation/phy.txt
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
29 That node describes an IP block (PHY provider) that implements 2 different PHYs.
33 PHY user node
37 phys : the phandle for the PHY device (used by the PHY subsystem; not to be
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| D | phy-hisi-inno-usb2.txt | 1 Device tree bindings for HiSilicon INNO USB2 PHY
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
16 The INNO USB2 PHY device should be a child node of peripheral controller that
17 contains the PHY configuration register, and each device suppports up to 2 PHY
18 ports which are represented as child nodes of INNO USB2 PHY device.
20 Required properties for PHY port node:
21 - reg: The PHY port instance number.
22 - #phy-cells: Defined by generic PHY bindings. Must be 0.
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| D | samsung-phy.txt | 14 In case of exynos5433 compatible PHY:
21 the PHY specifier identifies the PHY and its meaning is as follows:
27 supports additional fifth PHY:
30 Samsung EXYNOS SoC series Display Port PHY
39 - #phy-cells : from the generic PHY bindings, must be 0;
41 Samsung S5P/EXYNOS SoC series USB PHY
59 PHY module
64 The first phandle argument in the PHY specifier identifies the PHY, its
90 Then the PHY can be used in other nodes such as:
97 Refer to DT bindings documentation of particular PHY consumer devices for more
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| D | phy-stm32-usbphyc.txt | 1 STMicroelectronics STM32 USB HS PHY controller
3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
4 switch. It controls PHY configuration and status, and the UTMI+ switch that
5 selects either OTG or HOST controller for the second PHY port. It also sets
11 |_ PHY port#1 _________________ HOST controller
14 |_ PHY port#2 ----| |________________
41 - phy-supply: phandle to the regulator providing 3V3 power to the PHY,
43 - vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
44 - vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
45 - #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
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| D | ti-phy.txt | 1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
11 e.g. USB3 PHY and SATA PHY on OMAP5.
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
30 OMAP USB2 PHY
34 Should be "ti,dra7x-usb2" for the 1st instance of USB2 PHY on
36 Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY
48 - ctrl-module : phandle of the control module used by PHY driver to power on
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| D | qcom-dwc3-usb-phy.txt | 1 Qualcomm DWC3 HS AND SS PHY CONTROLLER
4 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
5 controllers. Each DWC3 PHY controller should have its own node.
9 - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
10 - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
11 - reg: offset and length of the DWC3 PHY controller register set
15 - clock-names: Should contain "ref" for the PHY reference clock
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| D | qcom-qusb2-phy.txt | 8 "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
9 "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
11 - reg: offset and length of the PHY register set.
20 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
31 added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
33 This property is applicable to only QUSB2 v2 PHY (sdm845).
38 This property is applicable to only QUSB2 v2 PHY (sdm845).
43 This property is applicable to only QUSB2 v2 PHY (sdm845).
49 This property is applicable to only QUSB2 v2 PHY (sdm845).
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| /Linux-v4.19/Documentation/networking/ |
| D | phy.txt | 3 PHY Abstraction Layer
10 PHY. The PHY concerns itself with negotiating link parameters with the link
17 the PHY management code with the network driver. This has resulted in large
23 accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
30 Basically, this layer is meant to provide an interface to PHY devices which
36 Most network devices are connected to a PHY by means of a management bus.
46 mii_id is the address on the bus for the PHY, and regnum is the register
73 between the clock line (RXC or TXC) and the data lines to let the PHY (clock
75 PHY library offers different types of PHY_INTERFACE_MODE_RGMII* values to let
76 the PHY driver and optionally the MAC driver, implement the required delay. The
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| D | dm9000.txt | 90 device, whether or not an external PHY is attached to the device and
109 The chip is connected to an external PHY.
118 Switch to using the simpler PHY polling method which does not
119 try and read the MII PHY state regularly. This is only available
120 when using the internal PHY. See the section on link state polling
124 "Force simple NSR based PHY polling" allows this flag to be
128 PHY Link state polling
133 depending on the version of the chip and on which PHY is being used.
135 For the internal PHY, the original (and currently default) method is
140 To reduce the overhead for the internal PHY, there is now the option
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| /Linux-v4.19/drivers/phy/samsung/ |
| D | Kconfig | 5 tristate "EXYNOS SoC series Display Port PHY driver"
11 Support for Display Port PHY found on Samsung EXYNOS SoCs.
14 tristate "S5P/EXYNOS SoC series MIPI CSI-2/DSI PHY driver"
24 bool "Exynos PCIe PHY driver"
28 Enable PCIe PHY support for Exynos SoC series.
29 This driver provides PHY interface for Exynos PCIe controller.
32 tristate "Samsung USB 2.0 PHY driver"
39 Enable this to support the Samsung USB 2.0 PHY driver for Samsung
40 SoCs. This driver provides the interface for USB 2.0 PHY. Support
64 Enable USB PHY support for S5PV210. This option requires that Samsung
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| /Linux-v4.19/drivers/phy/marvell/ |
| D | Kconfig | 11 tristate "Marvell Berlin SATA PHY driver"
15 Enable this to support the SATA PHY on Marvell Berlin SoCs.
18 tristate "Marvell Berlin USB PHY Driver"
22 Enable this to support the USB PHY on Marvell Berlin SoCs.
42 tristate "Marvell USB HSIC 28nm PHY Driver"
46 Enable this to support Marvell USB HSIC PHY driver for Marvell
47 SoC. This driver will do the PHY initialization and shutdown.
48 The PHY driver will be used by Marvell ehci driver.
53 tristate "Marvell USB 2.0 28nm PHY Driver"
57 Enable this to support Marvell USB 2.0 PHY driver for Marvell
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| /Linux-v4.19/drivers/phy/renesas/ |
| D | Kconfig | 5 tristate "Renesas R-Car generation 2 USB PHY driver"
9 Support for USB PHY found on Renesas R-Car generation 2 SoCs.
12 tristate "Renesas R-Car generation 3 PCIe PHY driver"
16 Support for the PCIe PHY found on Renesas R-Car generation 3 SoCs.
19 tristate "Renesas R-Car generation 3 USB 2.0 PHY driver"
26 Support for USB 2.0 PHY found on Renesas R-Car generation 3 SoCs.
29 tristate "Renesas R-Car generation 3 USB 3.0 PHY driver"
33 Support for USB 3.0 PHY found on Renesas R-Car generation 3 SoCs.
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| /Linux-v4.19/Documentation/devicetree/bindings/net/ |
| D | phy.txt | 1 PHY nodes
16 If the PHY reports an incorrect ID (or none at all) then the
17 "compatible" list may contain an entry with the correct PHY ID in the
28 - max-speed: Maximum PHY supported speed (10, 100, 1000...)
30 - broken-turn-around: If set, indicates the PHY device does not correctly
33 - enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to
36 - enet-phy-lane-no-swap: If set, indicates that PHY will disable swap of the
37 TX/RX lanes. This property allows the PHY to work correcly after e.g. wrong
49 - phy-is-integrated: If set, indicates that the PHY is integrated into the same
51 to ensure the integrated PHY is used. The absence of this property indicates
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| /Linux-v4.19/drivers/phy/mediatek/ |
| D | Kconfig | 5 tristate "MediaTek T-PHY Driver"
9 Say 'Y' here to add support for MediaTek T-PHY driver,
11 SATA, and meanwhile supports two version T-PHY which have
12 different banks layout, the T-PHY with shared banks between
17 tristate "MediaTek XS-PHY Driver"
21 Enable this to support the SuperSpeedPlus XS-PHY transceiver for
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| /Linux-v4.19/Documentation/devicetree/bindings/usb/ |
| D | usb-nop-xceiv.txt | 1 USB NOP PHY
8 - clocks: phandle to the PHY clock. Use as per Documentation/devicetree
14 - clock-frequency: the clock frequency (in Hz) that the PHY clock must
17 - vcc-supply: phandle to the regulator that provides power to the PHY.
40 hsusb1_phy is a NOP USB PHY device that gets its clock from an oscillator
41 and expects that clock to be configured to 19.2MHz by the NOP PHY driver.
42 hsusb1_vcc_regulator provides power to the PHY and GPIO 7 controls RESET.
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| /Linux-v4.19/drivers/net/phy/ |
| D | Kconfig | 2 # PHY Layer Configuration
177 PHYlink models the link between the PHY and MAC, allowing fixed
182 tristate "PHY Device support and infrastructure"
186 Ethernet controllers are usually attached to PHY
188 managing PHY devices.
199 Adds support for a set of LED trigger events per-PHY. Link
202 supported by the PHY and also a one common "link" trigger as a
209 for any speed known to the PHY.
212 comment "MII PHY device drivers"
233 Currently supports the Asix Electronics PHY found in the X-Surf 100
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| /Linux-v4.19/drivers/phy/hisilicon/ |
| D | Kconfig | 5 tristate "hi6220 USB PHY support"
11 Enable this to support the HISILICON HI6220 USB PHY.
25 tristate "HiSilicon INNO USB2 PHY support"
30 Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports
35 tristate "HIX5HD2 SATA PHY Driver"
40 Support for SATA PHY on Hisilicon hix5hd2 Soc.
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| /Linux-v4.19/Documentation/devicetree/bindings/ufs/ |
| D | ufs-qcom.txt | 1 * Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
3 UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
4 Each UFS PHY node should have its own node.
6 To bind UFS PHY with UFS host controller, the controller node should
7 contain a phandle reference to UFS PHY node.
15 - reg : should contain PHY register address space (mandatory),
19 - vdda-phy-supply : phandle to main PHY supply for analog domain
20 - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply
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| /Linux-v4.19/drivers/gpu/drm/msm/ |
| D | Kconfig | 71 bool "Enable DSI 28nm PHY driver in MSM DRM"
75 Choose this option if the 28nm DSI PHY is used on the platform.
78 bool "Enable DSI 20nm PHY driver in MSM DRM"
82 Choose this option if the 20nm DSI PHY is used on the platform.
85 bool "Enable DSI 28nm 8960 PHY driver in MSM DRM"
89 Choose this option if the 28nm DSI PHY 8960 variant is used on the
93 bool "Enable DSI 14nm PHY driver in MSM DRM (used by MSM8996/APQ8096)"
97 Choose this option if DSI PHY on 8996 is used on the platform.
100 bool "Enable DSI 10nm PHY driver in MSM DRM (used by SDM845)"
104 Choose this option if DSI PHY on SDM845 is used on the platform.
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