Searched refs:PHASE (Results 1 – 8 of 8) sorted by relevance
| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.h | 62 SRII(PHASE, DP_DTO, 0),\
63 SRII(PHASE, DP_DTO, 1),\
64 SRII(PHASE, DP_DTO, 2),\
65 SRII(PHASE, DP_DTO, 3),\
110 uint32_t PHASE[MAX_PIPES]; member
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| D | dce_clock_source.c | 653 REG_GET(PHASE[inst], DP_DTO0_PHASE, &phase); in dce110_get_d_to_pixel_rate_in_hz()
919 REG_WRITE(PHASE[inst], clock_kHz); in dce110_program_pix_clk()
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| /Linux-v4.19/sound/firewire/ |
| D | Kconfig | 102 * TerraTec PHASE 24 FW/PHASE X24 FW/PHASE 88 Rack FW
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| /Linux-v4.19/drivers/scsi/ |
| D | FlashPoint.c | 527 #define PHASE BIT(13) macro
1835 && !((RDW_HARPOON((ioport + hp_intstat)) & PHASE) in FlashPoint_HandleInterrupt()
1862 (PROG_HLT | RSEL | PHASE | BUS_FREE)); in FlashPoint_HandleInterrupt()
1898 (PHASE | IUNKWN | PROG_HLT)); in FlashPoint_HandleInterrupt()
2086 (PROG_HLT | TIMEOUT | SEL | BUS_FREE | PHASE | in FPT_SccbMgr_bad_isr()
2674 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2679 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2752 (PHASE | RESET)) in FPT_sres()
2834 while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) && in FPT_sres()
2844 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_SendMsg()
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| /Linux-v4.19/Documentation/networking/ |
| D | can.rst | 1172 [ tq TQ prop-seg PROP_SEG phase-seg1 PHASE-SEG1
1173 phase-seg2 PHASE-SEG2 [ sjw SJW ] ]
1176 [ dtq TQ dprop-seg PROP_SEG dphase-seg1 PHASE-SEG1
1177 dphase-seg2 PHASE-SEG2 [ dsjw SJW ] ]
1195 PHASE-SEG1 := { 1..8 }
1196 PHASE-SEG2 := { 1..8 }
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| /Linux-v4.19/Documentation/scsi/ |
| D | sym53c8xx_2.txt | 124 LOAD/STORE and handles PHASE MISMATCH from SCRIPTS for devices that
130 Chip SDMS BIOS Wide SCSI std. Max. sync SCRIPTS PHASE MISMATCH
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| D | ChangeLog.sym53c8xx | 341 to testing for a PHASE. SYMBIOS say this feature is working fine.
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| D | ncr53c8xx.txt | 1012 have detected an expected disconnection (BUS FREE PHASE). For this process
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