Searched refs:PESQI_CLK_CTRL_REG (Results 1 – 1 of 1) sorted by relevance
33 #define PESQI_CLK_CTRL_REG 0x10 macro181 val = readl(sqi->regs + PESQI_CLK_CTRL_REG); in pic32_sqi_set_clk_rate()185 writel(val, sqi->regs + PESQI_CLK_CTRL_REG); in pic32_sqi_set_clk_rate()188 return readl_poll_timeout(sqi->regs + PESQI_CLK_CTRL_REG, val, in pic32_sqi_set_clk_rate()334 pic32_setbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN); in pic32_sqi_prepare_hardware()455 pic32_clrbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN); in pic32_sqi_unprepare_hardware()
