Searched refs:PD0 (Results 1 – 17 of 17) sorted by relevance
| /Linux-v4.19/arch/arc/mm/ |
| D | tlbex.S | 244 ; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
245 ; (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])
265 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
268 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
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| /Linux-v4.19/Documentation/hwmon/ |
| D | max197 | 40 7,6 PD1,PD0 Clock and Power-Down modes
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| /Linux-v4.19/arch/arm/boot/dts/ |
| D | at91sam9m10g45ek.dts | 160 <AT91_PIOD 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD0 periph B */
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| D | sunxi-h3-h5.dtsi | 397 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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| D | at91sam9g45.dtsi | 718 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
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| D | sun9i-a80.dtsi | 957 pins = "PD0", "PD1", "PD2", "PD3",
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| D | sun6i-a31.dtsi | 664 pins = "PD0", "PD1", "PD2", "PD3",
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| D | sama5d3.dtsi | 692 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
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| /Linux-v4.19/arch/arm64/boot/dts/allwinner/ |
| D | sun50i-a64.dtsi | 441 pins = "PD0", "PD1", "PD2", "PD3";
466 pins = "PD0", "PD1";
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| /Linux-v4.19/drivers/pinctrl/sh-pfc/ |
| D | pfc-shx3.c | 327 PINMUX_GPIO(PD0),
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| D | pfc-sh7786.c | 449 PINMUX_GPIO(PD0),
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| D | pfc-sh7785.c | 713 PINMUX_GPIO(PD0),
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| D | pfc-sh7203.c | 764 PINMUX_GPIO(PD0),
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| D | pfc-sh7264.c | 1134 PINMUX_GPIO(PD0),
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| D | pfc-sh7269.c | 1510 PINMUX_GPIO(PD0),
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| /Linux-v4.19/arch/powerpc/boot/dts/ |
| D | kmeter1.dts | 227 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
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| /Linux-v4.19/drivers/iommu/ |
| D | msm_iommu_hw-8xxx.h | 601 #define SET_PD0(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v)
788 #define GET_PD0(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD0)
1168 #define PD0 (PD0_MASK << PD0_SHIFT) macro
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