Searched refs:PCH_DREF_CONTROL (Results 1 – 4 of 4) sorted by relevance
7999 val = I915_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()8057 I915_WRITE(PCH_DREF_CONTROL, val); in ironlake_init_pch_refclk()8058 POSTING_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()8073 I915_WRITE(PCH_DREF_CONTROL, val); in ironlake_init_pch_refclk()8074 POSTING_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()8084 I915_WRITE(PCH_DREF_CONTROL, val); in ironlake_init_pch_refclk()8085 POSTING_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()8098 I915_WRITE(PCH_DREF_CONTROL, val); in ironlake_init_pch_refclk()8099 POSTING_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()15175 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & in intel_modeset_init()
378 val = I915_READ(PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
7813 #define PCH_DREF_CONTROL _MMIO(0xC6200) macro
2223 MMIO_D(PCH_DREF_CONTROL, D_ALL); in init_generic_mmio_info()
