Searched refs:PCH_DPLL (Results 1 – 3 of 3) sorted by relevance
352 val = I915_READ(PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()392 I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()395 POSTING_READ(PCH_DPLL(id)); in ibx_pch_dpll_enable()403 I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()404 POSTING_READ(PCH_DPLL(id)); in ibx_pch_dpll_enable()421 I915_WRITE(PCH_DPLL(id), 0); in ibx_pch_dpll_disable()422 POSTING_READ(PCH_DPLL(id)); in ibx_pch_dpll_disable()
7801 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) macro
7979 u32 temp = I915_READ(PCH_DPLL(i)); in ironlake_init_pch_refclk()
