Searched refs:PACKET3_SET_CONFIG_REG_START (Results 1 – 14 of 14) sorted by relevance
241 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
263 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
342 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
460 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
1791 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_test_ring()1826 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_emit_fence()1907 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_test_ib()
1846 #define PACKET3_SET_CONFIG_REG_START 0x00002000 macro
2300 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in evergreen_packet3_check()2302 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || in evergreen_packet3_check()3421 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in evergreen_vm_packet3_check()3423 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || in evergreen_vm_packet3_check()
1270 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
3378 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_fence_ring_emit()3418 PACKET3_SET_CONFIG_REG_START) >> 2)); in si_ring_ib_execute()3444 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_ring_ib_execute()4618 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in si_vm_packet3_gfx_check()4620 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || in si_vm_packet3_gfx_check()
1783 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
1926 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
1666 #define PACKET3_SET_CONFIG_REG_START 0x00008000 macro
1437 PACKET3_SET_CONFIG_REG_START) >> 2)); in cayman_ring_ib_execute()
2939 PACKET3_SET_CONFIG_REG_START) >> 2)); in evergreen_ring_ib_execute()
