Searched refs:OUTMODE_MPEG2_PAR_GATED_CLK (Results 1 – 8 of 8) sorted by relevance
153 #define OUTMODE_MPEG2_PAR_GATED_CLK 1 macro
219 case OUTMODE_MPEG2_PAR_GATED_CLK: in to_fw_output_mode()1547 case OUTMODE_MPEG2_PAR_GATED_CLK: in dib9000_fw_set_output_mode()1573 case OUTMODE_MPEG2_PAR_GATED_CLK: in dib9000_fw_set_output_mode()2515 …tput_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK)) in dib9000_attach()
187 case OUTMODE_MPEG2_PAR_GATED_CLK: in dib7000p_set_output_mode()2641 case OUTMODE_MPEG2_PAR_GATED_CLK: in dib7090_set_output_mode()2751 …->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK)) in dib7000p_init()
203 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock in dib3000mc_set_output_mode()
167 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock in dib7000m_set_output_mode()
422 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock in dib8000_set_output_mode()1597 case OUTMODE_MPEG2_PAR_GATED_CLK: in dib8096p_set_output_mode()4446 …fg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK)) in dib8000_init()
2859 .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK,2886 .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK,2946 .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK,
922 .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK,
