1 /*
2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
3 * Steven J. Hill <sjhill@realitydiluted.com>
4 * Thomas Gleixner <tglx@linutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Info:
11 * Contains standard defines and IDs for NAND flash devices
12 *
13 * Changelog:
14 * See git changelog.
15 */
16 #ifndef __LINUX_MTD_RAWNAND_H
17 #define __LINUX_MTD_RAWNAND_H
18
19 #include <linux/wait.h>
20 #include <linux/spinlock.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/flashchip.h>
23 #include <linux/mtd/bbm.h>
24 #include <linux/of.h>
25 #include <linux/types.h>
26
27 struct nand_flash_dev;
28
29 /* Scan and identify a NAND device */
30 int nand_scan_with_ids(struct mtd_info *mtd, int max_chips,
31 struct nand_flash_dev *ids);
32
nand_scan(struct mtd_info * mtd,int max_chips)33 static inline int nand_scan(struct mtd_info *mtd, int max_chips)
34 {
35 return nand_scan_with_ids(mtd, max_chips, NULL);
36 }
37
38 /* Internal helper for board drivers which need to override command function */
39 void nand_wait_ready(struct mtd_info *mtd);
40
41 /* The maximum number of NAND chips in an array */
42 #define NAND_MAX_CHIPS 8
43
44 /*
45 * Constants for hardware specific CLE/ALE/NCE function
46 *
47 * These are bits which can be or'ed to set/clear multiple
48 * bits in one go.
49 */
50 /* Select the chip by setting nCE to low */
51 #define NAND_NCE 0x01
52 /* Select the command latch by setting CLE to high */
53 #define NAND_CLE 0x02
54 /* Select the address latch by setting ALE to high */
55 #define NAND_ALE 0x04
56
57 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
58 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
59 #define NAND_CTRL_CHANGE 0x80
60
61 /*
62 * Standard NAND flash commands
63 */
64 #define NAND_CMD_READ0 0
65 #define NAND_CMD_READ1 1
66 #define NAND_CMD_RNDOUT 5
67 #define NAND_CMD_PAGEPROG 0x10
68 #define NAND_CMD_READOOB 0x50
69 #define NAND_CMD_ERASE1 0x60
70 #define NAND_CMD_STATUS 0x70
71 #define NAND_CMD_SEQIN 0x80
72 #define NAND_CMD_RNDIN 0x85
73 #define NAND_CMD_READID 0x90
74 #define NAND_CMD_ERASE2 0xd0
75 #define NAND_CMD_PARAM 0xec
76 #define NAND_CMD_GET_FEATURES 0xee
77 #define NAND_CMD_SET_FEATURES 0xef
78 #define NAND_CMD_RESET 0xff
79
80 /* Extended commands for large page devices */
81 #define NAND_CMD_READSTART 0x30
82 #define NAND_CMD_RNDOUTSTART 0xE0
83 #define NAND_CMD_CACHEDPROG 0x15
84
85 #define NAND_CMD_NONE -1
86
87 /* Status bits */
88 #define NAND_STATUS_FAIL 0x01
89 #define NAND_STATUS_FAIL_N1 0x02
90 #define NAND_STATUS_TRUE_READY 0x20
91 #define NAND_STATUS_READY 0x40
92 #define NAND_STATUS_WP 0x80
93
94 #define NAND_DATA_IFACE_CHECK_ONLY -1
95
96 /*
97 * Constants for ECC_MODES
98 */
99 typedef enum {
100 NAND_ECC_NONE,
101 NAND_ECC_SOFT,
102 NAND_ECC_HW,
103 NAND_ECC_HW_SYNDROME,
104 NAND_ECC_HW_OOB_FIRST,
105 NAND_ECC_ON_DIE,
106 } nand_ecc_modes_t;
107
108 enum nand_ecc_algo {
109 NAND_ECC_UNKNOWN,
110 NAND_ECC_HAMMING,
111 NAND_ECC_BCH,
112 NAND_ECC_RS,
113 };
114
115 /*
116 * Constants for Hardware ECC
117 */
118 /* Reset Hardware ECC for read */
119 #define NAND_ECC_READ 0
120 /* Reset Hardware ECC for write */
121 #define NAND_ECC_WRITE 1
122 /* Enable Hardware ECC before syndrome is read back from flash */
123 #define NAND_ECC_READSYN 2
124
125 /*
126 * Enable generic NAND 'page erased' check. This check is only done when
127 * ecc.correct() returns -EBADMSG.
128 * Set this flag if your implementation does not fix bitflips in erased
129 * pages and you want to rely on the default implementation.
130 */
131 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
132 #define NAND_ECC_MAXIMIZE BIT(1)
133
134 /* Bit mask for flags passed to do_nand_read_ecc */
135 #define NAND_GET_DEVICE 0x80
136
137
138 /*
139 * Option constants for bizarre disfunctionality and real
140 * features.
141 */
142 /* Buswidth is 16 bit */
143 #define NAND_BUSWIDTH_16 0x00000002
144 /* Chip has cache program function */
145 #define NAND_CACHEPRG 0x00000008
146 /*
147 * Chip requires ready check on read (for auto-incremented sequential read).
148 * True only for small page devices; large page devices do not support
149 * autoincrement.
150 */
151 #define NAND_NEED_READRDY 0x00000100
152
153 /* Chip does not allow subpage writes */
154 #define NAND_NO_SUBPAGE_WRITE 0x00000200
155
156 /* Device is one of 'new' xD cards that expose fake nand command set */
157 #define NAND_BROKEN_XD 0x00000400
158
159 /* Device behaves just like nand, but is readonly */
160 #define NAND_ROM 0x00000800
161
162 /* Device supports subpage reads */
163 #define NAND_SUBPAGE_READ 0x00001000
164
165 /*
166 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
167 * patterns.
168 */
169 #define NAND_NEED_SCRAMBLING 0x00002000
170
171 /* Device needs 3rd row address cycle */
172 #define NAND_ROW_ADDR_3 0x00004000
173
174 /* Options valid for Samsung large page devices */
175 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
176
177 /* Macros to identify the above */
178 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
179 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
180 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
181
182 /* Non chip related options */
183 /* This option skips the bbt scan during initialization. */
184 #define NAND_SKIP_BBTSCAN 0x00010000
185 /* Chip may not exist, so silence any errors in scan */
186 #define NAND_SCAN_SILENT_NODEV 0x00040000
187 /*
188 * Autodetect nand buswidth with readid/onfi.
189 * This suppose the driver will configure the hardware in 8 bits mode
190 * when calling nand_scan_ident, and update its configuration
191 * before calling nand_scan_tail.
192 */
193 #define NAND_BUSWIDTH_AUTO 0x00080000
194 /*
195 * This option could be defined by controller drivers to protect against
196 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
197 */
198 #define NAND_USE_BOUNCE_BUFFER 0x00100000
199
200 /*
201 * In case your controller is implementing ->cmd_ctrl() and is relying on the
202 * default ->cmdfunc() implementation, you may want to let the core handle the
203 * tCCS delay which is required when a column change (RNDIN or RNDOUT) is
204 * requested.
205 * If your controller already takes care of this delay, you don't need to set
206 * this flag.
207 */
208 #define NAND_WAIT_TCCS 0x00200000
209
210 /*
211 * Whether the NAND chip is a boot medium. Drivers might use this information
212 * to select ECC algorithms supported by the boot ROM or similar restrictions.
213 */
214 #define NAND_IS_BOOT_MEDIUM 0x00400000
215
216 /* Options set by nand scan */
217 /* Nand scan has allocated controller struct */
218 #define NAND_CONTROLLER_ALLOC 0x80000000
219
220 /* Cell info constants */
221 #define NAND_CI_CHIPNR_MSK 0x03
222 #define NAND_CI_CELLTYPE_MSK 0x0C
223 #define NAND_CI_CELLTYPE_SHIFT 2
224
225 /* Keep gcc happy */
226 struct nand_chip;
227
228 /* ONFI version bits */
229 #define ONFI_VERSION_1_0 BIT(1)
230 #define ONFI_VERSION_2_0 BIT(2)
231 #define ONFI_VERSION_2_1 BIT(3)
232 #define ONFI_VERSION_2_2 BIT(4)
233 #define ONFI_VERSION_2_3 BIT(5)
234 #define ONFI_VERSION_3_0 BIT(6)
235 #define ONFI_VERSION_3_1 BIT(7)
236 #define ONFI_VERSION_3_2 BIT(8)
237 #define ONFI_VERSION_4_0 BIT(9)
238
239 /* ONFI features */
240 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
241 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
242
243 /* ONFI timing mode, used in both asynchronous and synchronous mode */
244 #define ONFI_TIMING_MODE_0 (1 << 0)
245 #define ONFI_TIMING_MODE_1 (1 << 1)
246 #define ONFI_TIMING_MODE_2 (1 << 2)
247 #define ONFI_TIMING_MODE_3 (1 << 3)
248 #define ONFI_TIMING_MODE_4 (1 << 4)
249 #define ONFI_TIMING_MODE_5 (1 << 5)
250 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
251
252 /* ONFI feature number/address */
253 #define ONFI_FEATURE_NUMBER 256
254 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
255
256 /* Vendor-specific feature address (Micron) */
257 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
258 #define ONFI_FEATURE_ON_DIE_ECC 0x90
259 #define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3)
260
261 /* ONFI subfeature parameters length */
262 #define ONFI_SUBFEATURE_PARAM_LEN 4
263
264 /* ONFI optional commands SET/GET FEATURES supported? */
265 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
266
267 struct nand_onfi_params {
268 /* rev info and features block */
269 /* 'O' 'N' 'F' 'I' */
270 u8 sig[4];
271 __le16 revision;
272 __le16 features;
273 __le16 opt_cmd;
274 u8 reserved0[2];
275 __le16 ext_param_page_length; /* since ONFI 2.1 */
276 u8 num_of_param_pages; /* since ONFI 2.1 */
277 u8 reserved1[17];
278
279 /* manufacturer information block */
280 char manufacturer[12];
281 char model[20];
282 u8 jedec_id;
283 __le16 date_code;
284 u8 reserved2[13];
285
286 /* memory organization block */
287 __le32 byte_per_page;
288 __le16 spare_bytes_per_page;
289 __le32 data_bytes_per_ppage;
290 __le16 spare_bytes_per_ppage;
291 __le32 pages_per_block;
292 __le32 blocks_per_lun;
293 u8 lun_count;
294 u8 addr_cycles;
295 u8 bits_per_cell;
296 __le16 bb_per_lun;
297 __le16 block_endurance;
298 u8 guaranteed_good_blocks;
299 __le16 guaranteed_block_endurance;
300 u8 programs_per_page;
301 u8 ppage_attr;
302 u8 ecc_bits;
303 u8 interleaved_bits;
304 u8 interleaved_ops;
305 u8 reserved3[13];
306
307 /* electrical parameter block */
308 u8 io_pin_capacitance_max;
309 __le16 async_timing_mode;
310 __le16 program_cache_timing_mode;
311 __le16 t_prog;
312 __le16 t_bers;
313 __le16 t_r;
314 __le16 t_ccs;
315 __le16 src_sync_timing_mode;
316 u8 src_ssync_features;
317 __le16 clk_pin_capacitance_typ;
318 __le16 io_pin_capacitance_typ;
319 __le16 input_pin_capacitance_typ;
320 u8 input_pin_capacitance_max;
321 u8 driver_strength_support;
322 __le16 t_int_r;
323 __le16 t_adl;
324 u8 reserved4[8];
325
326 /* vendor */
327 __le16 vendor_revision;
328 u8 vendor[88];
329
330 __le16 crc;
331 } __packed;
332
333 #define ONFI_CRC_BASE 0x4F4E
334
335 /* Extended ECC information Block Definition (since ONFI 2.1) */
336 struct onfi_ext_ecc_info {
337 u8 ecc_bits;
338 u8 codeword_size;
339 __le16 bb_per_lun;
340 __le16 block_endurance;
341 u8 reserved[2];
342 } __packed;
343
344 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
345 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
346 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
347 struct onfi_ext_section {
348 u8 type;
349 u8 length;
350 } __packed;
351
352 #define ONFI_EXT_SECTION_MAX 8
353
354 /* Extended Parameter Page Definition (since ONFI 2.1) */
355 struct onfi_ext_param_page {
356 __le16 crc;
357 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
358 u8 reserved0[10];
359 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
360
361 /*
362 * The actual size of the Extended Parameter Page is in
363 * @ext_param_page_length of nand_onfi_params{}.
364 * The following are the variable length sections.
365 * So we do not add any fields below. Please see the ONFI spec.
366 */
367 } __packed;
368
369 struct jedec_ecc_info {
370 u8 ecc_bits;
371 u8 codeword_size;
372 __le16 bb_per_lun;
373 __le16 block_endurance;
374 u8 reserved[2];
375 } __packed;
376
377 /* JEDEC features */
378 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
379
380 struct nand_jedec_params {
381 /* rev info and features block */
382 /* 'J' 'E' 'S' 'D' */
383 u8 sig[4];
384 __le16 revision;
385 __le16 features;
386 u8 opt_cmd[3];
387 __le16 sec_cmd;
388 u8 num_of_param_pages;
389 u8 reserved0[18];
390
391 /* manufacturer information block */
392 char manufacturer[12];
393 char model[20];
394 u8 jedec_id[6];
395 u8 reserved1[10];
396
397 /* memory organization block */
398 __le32 byte_per_page;
399 __le16 spare_bytes_per_page;
400 u8 reserved2[6];
401 __le32 pages_per_block;
402 __le32 blocks_per_lun;
403 u8 lun_count;
404 u8 addr_cycles;
405 u8 bits_per_cell;
406 u8 programs_per_page;
407 u8 multi_plane_addr;
408 u8 multi_plane_op_attr;
409 u8 reserved3[38];
410
411 /* electrical parameter block */
412 __le16 async_sdr_speed_grade;
413 __le16 toggle_ddr_speed_grade;
414 __le16 sync_ddr_speed_grade;
415 u8 async_sdr_features;
416 u8 toggle_ddr_features;
417 u8 sync_ddr_features;
418 __le16 t_prog;
419 __le16 t_bers;
420 __le16 t_r;
421 __le16 t_r_multi_plane;
422 __le16 t_ccs;
423 __le16 io_pin_capacitance_typ;
424 __le16 input_pin_capacitance_typ;
425 __le16 clk_pin_capacitance_typ;
426 u8 driver_strength_support;
427 __le16 t_adl;
428 u8 reserved4[36];
429
430 /* ECC and endurance block */
431 u8 guaranteed_good_blocks;
432 __le16 guaranteed_block_endurance;
433 struct jedec_ecc_info ecc_info[4];
434 u8 reserved5[29];
435
436 /* reserved */
437 u8 reserved6[148];
438
439 /* vendor */
440 __le16 vendor_rev_num;
441 u8 reserved7[88];
442
443 /* CRC for Parameter Page */
444 __le16 crc;
445 } __packed;
446
447 /**
448 * struct onfi_params - ONFI specific parameters that will be reused
449 * @version: ONFI version (BCD encoded), 0 if ONFI is not supported
450 * @tPROG: Page program time
451 * @tBERS: Block erase time
452 * @tR: Page read time
453 * @tCCS: Change column setup time
454 * @async_timing_mode: Supported asynchronous timing mode
455 * @vendor_revision: Vendor specific revision number
456 * @vendor: Vendor specific data
457 */
458 struct onfi_params {
459 int version;
460 u16 tPROG;
461 u16 tBERS;
462 u16 tR;
463 u16 tCCS;
464 u16 async_timing_mode;
465 u16 vendor_revision;
466 u8 vendor[88];
467 };
468
469 /**
470 * struct nand_parameters - NAND generic parameters from the parameter page
471 * @model: Model name
472 * @supports_set_get_features: The NAND chip supports setting/getting features
473 * @set_feature_list: Bitmap of features that can be set
474 * @get_feature_list: Bitmap of features that can be get
475 * @onfi: ONFI specific parameters
476 */
477 struct nand_parameters {
478 /* Generic parameters */
479 const char *model;
480 bool supports_set_get_features;
481 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
482 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);
483
484 /* ONFI parameters */
485 struct onfi_params *onfi;
486 };
487
488 /* The maximum expected count of bytes in the NAND ID sequence */
489 #define NAND_MAX_ID_LEN 8
490
491 /**
492 * struct nand_id - NAND id structure
493 * @data: buffer containing the id bytes.
494 * @len: ID length.
495 */
496 struct nand_id {
497 u8 data[NAND_MAX_ID_LEN];
498 int len;
499 };
500
501 /**
502 * struct nand_controller_ops - Controller operations
503 *
504 * @attach_chip: this method is called after the NAND detection phase after
505 * flash ID and MTD fields such as erase size, page size and OOB
506 * size have been set up. ECC requirements are available if
507 * provided by the NAND chip or device tree. Typically used to
508 * choose the appropriate ECC configuration and allocate
509 * associated resources.
510 * This hook is optional.
511 * @detach_chip: free all resources allocated/claimed in
512 * nand_controller_ops->attach_chip().
513 * This hook is optional.
514 */
515 struct nand_controller_ops {
516 int (*attach_chip)(struct nand_chip *chip);
517 void (*detach_chip)(struct nand_chip *chip);
518 };
519
520 /**
521 * struct nand_controller - Structure used to describe a NAND controller
522 *
523 * @lock: protection lock
524 * @active: the mtd device which holds the controller currently
525 * @wq: wait queue to sleep on if a NAND operation is in
526 * progress used instead of the per chip wait queue
527 * when a hw controller is available.
528 * @ops: NAND controller operations.
529 */
530 struct nand_controller {
531 spinlock_t lock;
532 struct nand_chip *active;
533 wait_queue_head_t wq;
534 const struct nand_controller_ops *ops;
535 };
536
nand_controller_init(struct nand_controller * nfc)537 static inline void nand_controller_init(struct nand_controller *nfc)
538 {
539 nfc->active = NULL;
540 spin_lock_init(&nfc->lock);
541 init_waitqueue_head(&nfc->wq);
542 }
543
544 /**
545 * struct nand_ecc_step_info - ECC step information of ECC engine
546 * @stepsize: data bytes per ECC step
547 * @strengths: array of supported strengths
548 * @nstrengths: number of supported strengths
549 */
550 struct nand_ecc_step_info {
551 int stepsize;
552 const int *strengths;
553 int nstrengths;
554 };
555
556 /**
557 * struct nand_ecc_caps - capability of ECC engine
558 * @stepinfos: array of ECC step information
559 * @nstepinfos: number of ECC step information
560 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
561 */
562 struct nand_ecc_caps {
563 const struct nand_ecc_step_info *stepinfos;
564 int nstepinfos;
565 int (*calc_ecc_bytes)(int step_size, int strength);
566 };
567
568 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
569 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
570 static const int __name##_strengths[] = { __VA_ARGS__ }; \
571 static const struct nand_ecc_step_info __name##_stepinfo = { \
572 .stepsize = __step, \
573 .strengths = __name##_strengths, \
574 .nstrengths = ARRAY_SIZE(__name##_strengths), \
575 }; \
576 static const struct nand_ecc_caps __name = { \
577 .stepinfos = &__name##_stepinfo, \
578 .nstepinfos = 1, \
579 .calc_ecc_bytes = __calc, \
580 }
581
582 /**
583 * struct nand_ecc_ctrl - Control structure for ECC
584 * @mode: ECC mode
585 * @algo: ECC algorithm
586 * @steps: number of ECC steps per page
587 * @size: data bytes per ECC step
588 * @bytes: ECC bytes per step
589 * @strength: max number of correctible bits per ECC step
590 * @total: total number of ECC bytes per page
591 * @prepad: padding information for syndrome based ECC generators
592 * @postpad: padding information for syndrome based ECC generators
593 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
594 * @priv: pointer to private ECC control data
595 * @calc_buf: buffer for calculated ECC, size is oobsize.
596 * @code_buf: buffer for ECC read from flash, size is oobsize.
597 * @hwctl: function to control hardware ECC generator. Must only
598 * be provided if an hardware ECC is available
599 * @calculate: function for ECC calculation or readback from ECC hardware
600 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
601 * Should return a positive number representing the number of
602 * corrected bitflips, -EBADMSG if the number of bitflips exceed
603 * ECC strength, or any other error code if the error is not
604 * directly related to correction.
605 * If -EBADMSG is returned the input buffers should be left
606 * untouched.
607 * @read_page_raw: function to read a raw page without ECC. This function
608 * should hide the specific layout used by the ECC
609 * controller and always return contiguous in-band and
610 * out-of-band data even if they're not stored
611 * contiguously on the NAND chip (e.g.
612 * NAND_ECC_HW_SYNDROME interleaves in-band and
613 * out-of-band data).
614 * @write_page_raw: function to write a raw page without ECC. This function
615 * should hide the specific layout used by the ECC
616 * controller and consider the passed data as contiguous
617 * in-band and out-of-band data. ECC controller is
618 * responsible for doing the appropriate transformations
619 * to adapt to its specific layout (e.g.
620 * NAND_ECC_HW_SYNDROME interleaves in-band and
621 * out-of-band data).
622 * @read_page: function to read a page according to the ECC generator
623 * requirements; returns maximum number of bitflips corrected in
624 * any single ECC step, -EIO hw error
625 * @read_subpage: function to read parts of the page covered by ECC;
626 * returns same as read_page()
627 * @write_subpage: function to write parts of the page covered by ECC.
628 * @write_page: function to write a page according to the ECC generator
629 * requirements.
630 * @write_oob_raw: function to write chip OOB data without ECC
631 * @read_oob_raw: function to read chip OOB data without ECC
632 * @read_oob: function to read chip OOB data
633 * @write_oob: function to write chip OOB data
634 */
635 struct nand_ecc_ctrl {
636 nand_ecc_modes_t mode;
637 enum nand_ecc_algo algo;
638 int steps;
639 int size;
640 int bytes;
641 int total;
642 int strength;
643 int prepad;
644 int postpad;
645 unsigned int options;
646 void *priv;
647 u8 *calc_buf;
648 u8 *code_buf;
649 void (*hwctl)(struct mtd_info *mtd, int mode);
650 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
651 uint8_t *ecc_code);
652 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
653 uint8_t *calc_ecc);
654 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
655 uint8_t *buf, int oob_required, int page);
656 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
657 const uint8_t *buf, int oob_required, int page);
658 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
659 uint8_t *buf, int oob_required, int page);
660 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
661 uint32_t offs, uint32_t len, uint8_t *buf, int page);
662 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
663 uint32_t offset, uint32_t data_len,
664 const uint8_t *data_buf, int oob_required, int page);
665 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
666 const uint8_t *buf, int oob_required, int page);
667 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
668 int page);
669 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
670 int page);
671 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
672 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
673 int page);
674 };
675
676 /**
677 * struct nand_sdr_timings - SDR NAND chip timings
678 *
679 * This struct defines the timing requirements of a SDR NAND chip.
680 * These information can be found in every NAND datasheets and the timings
681 * meaning are described in the ONFI specifications:
682 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
683 * Parameters)
684 *
685 * All these timings are expressed in picoseconds.
686 *
687 * @tBERS_max: Block erase time
688 * @tCCS_min: Change column setup time
689 * @tPROG_max: Page program time
690 * @tR_max: Page read time
691 * @tALH_min: ALE hold time
692 * @tADL_min: ALE to data loading time
693 * @tALS_min: ALE setup time
694 * @tAR_min: ALE to RE# delay
695 * @tCEA_max: CE# access time
696 * @tCEH_min: CE# high hold time
697 * @tCH_min: CE# hold time
698 * @tCHZ_max: CE# high to output hi-Z
699 * @tCLH_min: CLE hold time
700 * @tCLR_min: CLE to RE# delay
701 * @tCLS_min: CLE setup time
702 * @tCOH_min: CE# high to output hold
703 * @tCS_min: CE# setup time
704 * @tDH_min: Data hold time
705 * @tDS_min: Data setup time
706 * @tFEAT_max: Busy time for Set Features and Get Features
707 * @tIR_min: Output hi-Z to RE# low
708 * @tITC_max: Interface and Timing Mode Change time
709 * @tRC_min: RE# cycle time
710 * @tREA_max: RE# access time
711 * @tREH_min: RE# high hold time
712 * @tRHOH_min: RE# high to output hold
713 * @tRHW_min: RE# high to WE# low
714 * @tRHZ_max: RE# high to output hi-Z
715 * @tRLOH_min: RE# low to output hold
716 * @tRP_min: RE# pulse width
717 * @tRR_min: Ready to RE# low (data only)
718 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
719 * rising edge of R/B#.
720 * @tWB_max: WE# high to SR[6] low
721 * @tWC_min: WE# cycle time
722 * @tWH_min: WE# high hold time
723 * @tWHR_min: WE# high to RE# low
724 * @tWP_min: WE# pulse width
725 * @tWW_min: WP# transition to WE# low
726 */
727 struct nand_sdr_timings {
728 u64 tBERS_max;
729 u32 tCCS_min;
730 u64 tPROG_max;
731 u64 tR_max;
732 u32 tALH_min;
733 u32 tADL_min;
734 u32 tALS_min;
735 u32 tAR_min;
736 u32 tCEA_max;
737 u32 tCEH_min;
738 u32 tCH_min;
739 u32 tCHZ_max;
740 u32 tCLH_min;
741 u32 tCLR_min;
742 u32 tCLS_min;
743 u32 tCOH_min;
744 u32 tCS_min;
745 u32 tDH_min;
746 u32 tDS_min;
747 u32 tFEAT_max;
748 u32 tIR_min;
749 u32 tITC_max;
750 u32 tRC_min;
751 u32 tREA_max;
752 u32 tREH_min;
753 u32 tRHOH_min;
754 u32 tRHW_min;
755 u32 tRHZ_max;
756 u32 tRLOH_min;
757 u32 tRP_min;
758 u32 tRR_min;
759 u64 tRST_max;
760 u32 tWB_max;
761 u32 tWC_min;
762 u32 tWH_min;
763 u32 tWHR_min;
764 u32 tWP_min;
765 u32 tWW_min;
766 };
767
768 /**
769 * enum nand_data_interface_type - NAND interface timing type
770 * @NAND_SDR_IFACE: Single Data Rate interface
771 */
772 enum nand_data_interface_type {
773 NAND_SDR_IFACE,
774 };
775
776 /**
777 * struct nand_data_interface - NAND interface timing
778 * @type: type of the timing
779 * @timings: The timing, type according to @type
780 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
781 */
782 struct nand_data_interface {
783 enum nand_data_interface_type type;
784 union {
785 struct nand_sdr_timings sdr;
786 } timings;
787 };
788
789 /**
790 * nand_get_sdr_timings - get SDR timing from data interface
791 * @conf: The data interface
792 */
793 static inline const struct nand_sdr_timings *
nand_get_sdr_timings(const struct nand_data_interface * conf)794 nand_get_sdr_timings(const struct nand_data_interface *conf)
795 {
796 if (conf->type != NAND_SDR_IFACE)
797 return ERR_PTR(-EINVAL);
798
799 return &conf->timings.sdr;
800 }
801
802 /**
803 * struct nand_manufacturer_ops - NAND Manufacturer operations
804 * @detect: detect the NAND memory organization and capabilities
805 * @init: initialize all vendor specific fields (like the ->read_retry()
806 * implementation) if any.
807 * @cleanup: the ->init() function may have allocated resources, ->cleanup()
808 * is here to let vendor specific code release those resources.
809 * @fixup_onfi_param_page: apply vendor specific fixups to the ONFI parameter
810 * page. This is called after the checksum is verified.
811 */
812 struct nand_manufacturer_ops {
813 void (*detect)(struct nand_chip *chip);
814 int (*init)(struct nand_chip *chip);
815 void (*cleanup)(struct nand_chip *chip);
816 void (*fixup_onfi_param_page)(struct nand_chip *chip,
817 struct nand_onfi_params *p);
818 };
819
820 /**
821 * struct nand_op_cmd_instr - Definition of a command instruction
822 * @opcode: the command to issue in one cycle
823 */
824 struct nand_op_cmd_instr {
825 u8 opcode;
826 };
827
828 /**
829 * struct nand_op_addr_instr - Definition of an address instruction
830 * @naddrs: length of the @addrs array
831 * @addrs: array containing the address cycles to issue
832 */
833 struct nand_op_addr_instr {
834 unsigned int naddrs;
835 const u8 *addrs;
836 };
837
838 /**
839 * struct nand_op_data_instr - Definition of a data instruction
840 * @len: number of data bytes to move
841 * @buf: buffer to fill
842 * @buf.in: buffer to fill when reading from the NAND chip
843 * @buf.out: buffer to read from when writing to the NAND chip
844 * @force_8bit: force 8-bit access
845 *
846 * Please note that "in" and "out" are inverted from the ONFI specification
847 * and are from the controller perspective, so a "in" is a read from the NAND
848 * chip while a "out" is a write to the NAND chip.
849 */
850 struct nand_op_data_instr {
851 unsigned int len;
852 union {
853 void *in;
854 const void *out;
855 } buf;
856 bool force_8bit;
857 };
858
859 /**
860 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
861 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms
862 */
863 struct nand_op_waitrdy_instr {
864 unsigned int timeout_ms;
865 };
866
867 /**
868 * enum nand_op_instr_type - Definition of all instruction types
869 * @NAND_OP_CMD_INSTR: command instruction
870 * @NAND_OP_ADDR_INSTR: address instruction
871 * @NAND_OP_DATA_IN_INSTR: data in instruction
872 * @NAND_OP_DATA_OUT_INSTR: data out instruction
873 * @NAND_OP_WAITRDY_INSTR: wait ready instruction
874 */
875 enum nand_op_instr_type {
876 NAND_OP_CMD_INSTR,
877 NAND_OP_ADDR_INSTR,
878 NAND_OP_DATA_IN_INSTR,
879 NAND_OP_DATA_OUT_INSTR,
880 NAND_OP_WAITRDY_INSTR,
881 };
882
883 /**
884 * struct nand_op_instr - Instruction object
885 * @type: the instruction type
886 * @ctx: extra data associated to the instruction. You'll have to use the
887 * appropriate element depending on @type
888 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
889 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
890 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
891 * or %NAND_OP_DATA_OUT_INSTR
892 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
893 * @delay_ns: delay the controller should apply after the instruction has been
894 * issued on the bus. Most modern controllers have internal timings
895 * control logic, and in this case, the controller driver can ignore
896 * this field.
897 */
898 struct nand_op_instr {
899 enum nand_op_instr_type type;
900 union {
901 struct nand_op_cmd_instr cmd;
902 struct nand_op_addr_instr addr;
903 struct nand_op_data_instr data;
904 struct nand_op_waitrdy_instr waitrdy;
905 } ctx;
906 unsigned int delay_ns;
907 };
908
909 /*
910 * Special handling must be done for the WAITRDY timeout parameter as it usually
911 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
912 * tBERS (during an erase) which all of them are u64 values that cannot be
913 * divided by usual kernel macros and must be handled with the special
914 * DIV_ROUND_UP_ULL() macro.
915 *
916 * Cast to type of dividend is needed here to guarantee that the result won't
917 * be an unsigned long long when the dividend is an unsigned long (or smaller),
918 * which is what the compiler does when it sees ternary operator with 2
919 * different return types (picks the largest type to make sure there's no
920 * loss).
921 */
922 #define __DIVIDE(dividend, divisor) ({ \
923 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
924 DIV_ROUND_UP(dividend, divisor) : \
925 DIV_ROUND_UP_ULL(dividend, divisor)); \
926 })
927 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
928 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
929
930 #define NAND_OP_CMD(id, ns) \
931 { \
932 .type = NAND_OP_CMD_INSTR, \
933 .ctx.cmd.opcode = id, \
934 .delay_ns = ns, \
935 }
936
937 #define NAND_OP_ADDR(ncycles, cycles, ns) \
938 { \
939 .type = NAND_OP_ADDR_INSTR, \
940 .ctx.addr = { \
941 .naddrs = ncycles, \
942 .addrs = cycles, \
943 }, \
944 .delay_ns = ns, \
945 }
946
947 #define NAND_OP_DATA_IN(l, b, ns) \
948 { \
949 .type = NAND_OP_DATA_IN_INSTR, \
950 .ctx.data = { \
951 .len = l, \
952 .buf.in = b, \
953 .force_8bit = false, \
954 }, \
955 .delay_ns = ns, \
956 }
957
958 #define NAND_OP_DATA_OUT(l, b, ns) \
959 { \
960 .type = NAND_OP_DATA_OUT_INSTR, \
961 .ctx.data = { \
962 .len = l, \
963 .buf.out = b, \
964 .force_8bit = false, \
965 }, \
966 .delay_ns = ns, \
967 }
968
969 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \
970 { \
971 .type = NAND_OP_DATA_IN_INSTR, \
972 .ctx.data = { \
973 .len = l, \
974 .buf.in = b, \
975 .force_8bit = true, \
976 }, \
977 .delay_ns = ns, \
978 }
979
980 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \
981 { \
982 .type = NAND_OP_DATA_OUT_INSTR, \
983 .ctx.data = { \
984 .len = l, \
985 .buf.out = b, \
986 .force_8bit = true, \
987 }, \
988 .delay_ns = ns, \
989 }
990
991 #define NAND_OP_WAIT_RDY(tout_ms, ns) \
992 { \
993 .type = NAND_OP_WAITRDY_INSTR, \
994 .ctx.waitrdy.timeout_ms = tout_ms, \
995 .delay_ns = ns, \
996 }
997
998 /**
999 * struct nand_subop - a sub operation
1000 * @instrs: array of instructions
1001 * @ninstrs: length of the @instrs array
1002 * @first_instr_start_off: offset to start from for the first instruction
1003 * of the sub-operation
1004 * @last_instr_end_off: offset to end at (excluded) for the last instruction
1005 * of the sub-operation
1006 *
1007 * Both @first_instr_start_off and @last_instr_end_off only apply to data or
1008 * address instructions.
1009 *
1010 * When an operation cannot be handled as is by the NAND controller, it will
1011 * be split by the parser into sub-operations which will be passed to the
1012 * controller driver.
1013 */
1014 struct nand_subop {
1015 const struct nand_op_instr *instrs;
1016 unsigned int ninstrs;
1017 unsigned int first_instr_start_off;
1018 unsigned int last_instr_end_off;
1019 };
1020
1021 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
1022 unsigned int op_id);
1023 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
1024 unsigned int op_id);
1025 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
1026 unsigned int op_id);
1027 unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
1028 unsigned int op_id);
1029
1030 /**
1031 * struct nand_op_parser_addr_constraints - Constraints for address instructions
1032 * @maxcycles: maximum number of address cycles the controller can issue in a
1033 * single step
1034 */
1035 struct nand_op_parser_addr_constraints {
1036 unsigned int maxcycles;
1037 };
1038
1039 /**
1040 * struct nand_op_parser_data_constraints - Constraints for data instructions
1041 * @maxlen: maximum data length that the controller can handle in a single step
1042 */
1043 struct nand_op_parser_data_constraints {
1044 unsigned int maxlen;
1045 };
1046
1047 /**
1048 * struct nand_op_parser_pattern_elem - One element of a pattern
1049 * @type: the instructuction type
1050 * @optional: whether this element of the pattern is optional or mandatory
1051 * @ctx: address or data constraint
1052 * @ctx.addr: address constraint (number of cycles)
1053 * @ctx.data: data constraint (data length)
1054 */
1055 struct nand_op_parser_pattern_elem {
1056 enum nand_op_instr_type type;
1057 bool optional;
1058 union {
1059 struct nand_op_parser_addr_constraints addr;
1060 struct nand_op_parser_data_constraints data;
1061 } ctx;
1062 };
1063
1064 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \
1065 { \
1066 .type = NAND_OP_CMD_INSTR, \
1067 .optional = _opt, \
1068 }
1069
1070 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \
1071 { \
1072 .type = NAND_OP_ADDR_INSTR, \
1073 .optional = _opt, \
1074 .ctx.addr.maxcycles = _maxcycles, \
1075 }
1076
1077 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \
1078 { \
1079 .type = NAND_OP_DATA_IN_INSTR, \
1080 .optional = _opt, \
1081 .ctx.data.maxlen = _maxlen, \
1082 }
1083
1084 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \
1085 { \
1086 .type = NAND_OP_DATA_OUT_INSTR, \
1087 .optional = _opt, \
1088 .ctx.data.maxlen = _maxlen, \
1089 }
1090
1091 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \
1092 { \
1093 .type = NAND_OP_WAITRDY_INSTR, \
1094 .optional = _opt, \
1095 }
1096
1097 /**
1098 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
1099 * @elems: array of pattern elements
1100 * @nelems: number of pattern elements in @elems array
1101 * @exec: the function that will issue a sub-operation
1102 *
1103 * A pattern is a list of elements, each element reprensenting one instruction
1104 * with its constraints. The pattern itself is used by the core to match NAND
1105 * chip operation with NAND controller operations.
1106 * Once a match between a NAND controller operation pattern and a NAND chip
1107 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
1108 * hook is called so that the controller driver can issue the operation on the
1109 * bus.
1110 *
1111 * Controller drivers should declare as many patterns as they support and pass
1112 * this list of patterns (created with the help of the following macro) to
1113 * the nand_op_parser_exec_op() helper.
1114 */
1115 struct nand_op_parser_pattern {
1116 const struct nand_op_parser_pattern_elem *elems;
1117 unsigned int nelems;
1118 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
1119 };
1120
1121 #define NAND_OP_PARSER_PATTERN(_exec, ...) \
1122 { \
1123 .exec = _exec, \
1124 .elems = (struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \
1125 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \
1126 sizeof(struct nand_op_parser_pattern_elem), \
1127 }
1128
1129 /**
1130 * struct nand_op_parser - NAND controller operation parser descriptor
1131 * @patterns: array of supported patterns
1132 * @npatterns: length of the @patterns array
1133 *
1134 * The parser descriptor is just an array of supported patterns which will be
1135 * iterated by nand_op_parser_exec_op() everytime it tries to execute an
1136 * NAND operation (or tries to determine if a specific operation is supported).
1137 *
1138 * It is worth mentioning that patterns will be tested in their declaration
1139 * order, and the first match will be taken, so it's important to order patterns
1140 * appropriately so that simple/inefficient patterns are placed at the end of
1141 * the list. Usually, this is where you put single instruction patterns.
1142 */
1143 struct nand_op_parser {
1144 const struct nand_op_parser_pattern *patterns;
1145 unsigned int npatterns;
1146 };
1147
1148 #define NAND_OP_PARSER(...) \
1149 { \
1150 .patterns = (struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \
1151 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \
1152 sizeof(struct nand_op_parser_pattern), \
1153 }
1154
1155 /**
1156 * struct nand_operation - NAND operation descriptor
1157 * @instrs: array of instructions to execute
1158 * @ninstrs: length of the @instrs array
1159 *
1160 * The actual operation structure that will be passed to chip->exec_op().
1161 */
1162 struct nand_operation {
1163 const struct nand_op_instr *instrs;
1164 unsigned int ninstrs;
1165 };
1166
1167 #define NAND_OPERATION(_instrs) \
1168 { \
1169 .instrs = _instrs, \
1170 .ninstrs = ARRAY_SIZE(_instrs), \
1171 }
1172
1173 int nand_op_parser_exec_op(struct nand_chip *chip,
1174 const struct nand_op_parser *parser,
1175 const struct nand_operation *op, bool check_only);
1176
1177 /**
1178 * struct nand_chip - NAND Private Flash Chip Data
1179 * @mtd: MTD device registered to the MTD framework
1180 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
1181 * flash device
1182 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
1183 * flash device.
1184 * @read_byte: [REPLACEABLE] read one byte from the chip
1185 * @read_word: [REPLACEABLE] read one word from the chip
1186 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
1187 * low 8 I/O lines
1188 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
1189 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
1190 * @select_chip: [REPLACEABLE] select chip nr
1191 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
1192 * @block_markbad: [REPLACEABLE] mark a block bad
1193 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
1194 * ALE/CLE/nCE. Also used to write command and address
1195 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
1196 * device ready/busy line. If set to NULL no access to
1197 * ready/busy is available and the ready/busy information
1198 * is read from the chip status register.
1199 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
1200 * commands to the chip.
1201 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
1202 * ready.
1203 * @exec_op: controller specific method to execute NAND operations.
1204 * This method replaces ->cmdfunc(),
1205 * ->{read,write}_{buf,byte,word}(), ->dev_ready() and
1206 * ->waifunc().
1207 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
1208 * setting the read-retry mode. Mostly needed for MLC NAND.
1209 * @ecc: [BOARDSPECIFIC] ECC control structure
1210 * @buf_align: minimum buffer alignment required by a platform
1211 * @dummy_controller: dummy controller implementation for drivers that can
1212 * only control a single chip
1213 * @erase: [REPLACEABLE] erase function
1214 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
1215 * data from array to read regs (tR).
1216 * @state: [INTERN] the current state of the NAND device
1217 * @oob_poi: "poison value buffer," used for laying out OOB data
1218 * before writing
1219 * @page_shift: [INTERN] number of address bits in a page (column
1220 * address bits).
1221 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
1222 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
1223 * @chip_shift: [INTERN] number of address bits in one chip
1224 * @options: [BOARDSPECIFIC] various chip options. They can partly
1225 * be set to inform nand_scan about special functionality.
1226 * See the defines for further explanation.
1227 * @bbt_options: [INTERN] bad block specific options. All options used
1228 * here must come from bbm.h. By default, these options
1229 * will be copied to the appropriate nand_bbt_descr's.
1230 * @badblockpos: [INTERN] position of the bad block marker in the oob
1231 * area.
1232 * @badblockbits: [INTERN] minimum number of set bits in a good block's
1233 * bad block marker position; i.e., BBM == 11110111b is
1234 * not bad when badblockbits == 7
1235 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
1236 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
1237 * Minimum amount of bit errors per @ecc_step_ds guaranteed
1238 * to be correctable. If unknown, set to zero.
1239 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
1240 * also from the datasheet. It is the recommended ECC step
1241 * size, if known; if unknown, set to zero.
1242 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
1243 * set to the actually used ONFI mode if the chip is
1244 * ONFI compliant or deduced from the datasheet if
1245 * the NAND chip is not ONFI compliant.
1246 * @numchips: [INTERN] number of physical chips
1247 * @chipsize: [INTERN] the size of one chip for multichip arrays
1248 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
1249 * @data_buf: [INTERN] buffer for data, size is (page size + oobsize).
1250 * @pagebuf: [INTERN] holds the pagenumber which is currently in
1251 * data_buf.
1252 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
1253 * currently in data_buf.
1254 * @subpagesize: [INTERN] holds the subpagesize
1255 * @id: [INTERN] holds NAND ID
1256 * @parameters: [INTERN] holds generic parameters under an easily
1257 * readable form.
1258 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a
1259 * this nand device will encounter their life times.
1260 * @blocks_per_die: [INTERN] The number of PEBs in a die
1261 * @data_interface: [INTERN] NAND interface timing information
1262 * @read_retries: [INTERN] the number of read retry modes supported
1263 * @set_features: [REPLACEABLE] set the NAND chip features
1264 * @get_features: [REPLACEABLE] get the NAND chip features
1265 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
1266 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
1267 * means the configuration should not be applied but
1268 * only checked.
1269 * @bbt: [INTERN] bad block table pointer
1270 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
1271 * lookup.
1272 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
1273 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
1274 * bad block scan.
1275 * @controller: [REPLACEABLE] a pointer to a hardware controller
1276 * structure which is shared among multiple independent
1277 * devices.
1278 * @priv: [OPTIONAL] pointer to private chip data
1279 * @manufacturer: [INTERN] Contains manufacturer information
1280 * @manufacturer.desc: [INTERN] Contains manufacturer's description
1281 * @manufacturer.priv: [INTERN] Contains manufacturer private information
1282 */
1283
1284 struct nand_chip {
1285 struct mtd_info mtd;
1286 void __iomem *IO_ADDR_R;
1287 void __iomem *IO_ADDR_W;
1288
1289 uint8_t (*read_byte)(struct mtd_info *mtd);
1290 u16 (*read_word)(struct mtd_info *mtd);
1291 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
1292 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1293 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1294 void (*select_chip)(struct mtd_info *mtd, int chip);
1295 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
1296 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
1297 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1298 int (*dev_ready)(struct mtd_info *mtd);
1299 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
1300 int page_addr);
1301 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
1302 int (*exec_op)(struct nand_chip *chip,
1303 const struct nand_operation *op,
1304 bool check_only);
1305 int (*erase)(struct mtd_info *mtd, int page);
1306 int (*set_features)(struct mtd_info *mtd, struct nand_chip *chip,
1307 int feature_addr, uint8_t *subfeature_para);
1308 int (*get_features)(struct mtd_info *mtd, struct nand_chip *chip,
1309 int feature_addr, uint8_t *subfeature_para);
1310 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
1311 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
1312 const struct nand_data_interface *conf);
1313
1314 int chip_delay;
1315 unsigned int options;
1316 unsigned int bbt_options;
1317
1318 int page_shift;
1319 int phys_erase_shift;
1320 int bbt_erase_shift;
1321 int chip_shift;
1322 int numchips;
1323 uint64_t chipsize;
1324 int pagemask;
1325 u8 *data_buf;
1326 int pagebuf;
1327 unsigned int pagebuf_bitflips;
1328 int subpagesize;
1329 uint8_t bits_per_cell;
1330 uint16_t ecc_strength_ds;
1331 uint16_t ecc_step_ds;
1332 int onfi_timing_mode_default;
1333 int badblockpos;
1334 int badblockbits;
1335
1336 struct nand_id id;
1337 struct nand_parameters parameters;
1338 u16 max_bb_per_die;
1339 u32 blocks_per_die;
1340
1341 struct nand_data_interface data_interface;
1342
1343 int read_retries;
1344
1345 flstate_t state;
1346
1347 uint8_t *oob_poi;
1348 struct nand_controller *controller;
1349
1350 struct nand_ecc_ctrl ecc;
1351 unsigned long buf_align;
1352 struct nand_controller dummy_controller;
1353
1354 uint8_t *bbt;
1355 struct nand_bbt_descr *bbt_td;
1356 struct nand_bbt_descr *bbt_md;
1357
1358 struct nand_bbt_descr *badblock_pattern;
1359
1360 void *priv;
1361
1362 struct {
1363 const struct nand_manufacturer *desc;
1364 void *priv;
1365 } manufacturer;
1366 };
1367
nand_exec_op(struct nand_chip * chip,const struct nand_operation * op)1368 static inline int nand_exec_op(struct nand_chip *chip,
1369 const struct nand_operation *op)
1370 {
1371 if (!chip->exec_op)
1372 return -ENOTSUPP;
1373
1374 return chip->exec_op(chip, op, false);
1375 }
1376
1377 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
1378 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
1379
nand_set_flash_node(struct nand_chip * chip,struct device_node * np)1380 static inline void nand_set_flash_node(struct nand_chip *chip,
1381 struct device_node *np)
1382 {
1383 mtd_set_of_node(&chip->mtd, np);
1384 }
1385
nand_get_flash_node(struct nand_chip * chip)1386 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1387 {
1388 return mtd_get_of_node(&chip->mtd);
1389 }
1390
mtd_to_nand(struct mtd_info * mtd)1391 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1392 {
1393 return container_of(mtd, struct nand_chip, mtd);
1394 }
1395
nand_to_mtd(struct nand_chip * chip)1396 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1397 {
1398 return &chip->mtd;
1399 }
1400
nand_get_controller_data(struct nand_chip * chip)1401 static inline void *nand_get_controller_data(struct nand_chip *chip)
1402 {
1403 return chip->priv;
1404 }
1405
nand_set_controller_data(struct nand_chip * chip,void * priv)1406 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1407 {
1408 chip->priv = priv;
1409 }
1410
nand_set_manufacturer_data(struct nand_chip * chip,void * priv)1411 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1412 void *priv)
1413 {
1414 chip->manufacturer.priv = priv;
1415 }
1416
nand_get_manufacturer_data(struct nand_chip * chip)1417 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1418 {
1419 return chip->manufacturer.priv;
1420 }
1421
1422 /*
1423 * NAND Flash Manufacturer ID Codes
1424 */
1425 #define NAND_MFR_TOSHIBA 0x98
1426 #define NAND_MFR_ESMT 0xc8
1427 #define NAND_MFR_SAMSUNG 0xec
1428 #define NAND_MFR_FUJITSU 0x04
1429 #define NAND_MFR_NATIONAL 0x8f
1430 #define NAND_MFR_RENESAS 0x07
1431 #define NAND_MFR_STMICRO 0x20
1432 #define NAND_MFR_HYNIX 0xad
1433 #define NAND_MFR_MICRON 0x2c
1434 #define NAND_MFR_AMD 0x01
1435 #define NAND_MFR_MACRONIX 0xc2
1436 #define NAND_MFR_EON 0x92
1437 #define NAND_MFR_SANDISK 0x45
1438 #define NAND_MFR_INTEL 0x89
1439 #define NAND_MFR_ATO 0x9b
1440 #define NAND_MFR_WINBOND 0xef
1441
1442
1443 /*
1444 * A helper for defining older NAND chips where the second ID byte fully
1445 * defined the chip, including the geometry (chip size, eraseblock size, page
1446 * size). All these chips have 512 bytes NAND page size.
1447 */
1448 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1449 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1450 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1451
1452 /*
1453 * A helper for defining newer chips which report their page size and
1454 * eraseblock size via the extended ID bytes.
1455 *
1456 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1457 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1458 * device ID now only represented a particular total chip size (and voltage,
1459 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1460 * using the same device ID.
1461 */
1462 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1463 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1464 .options = (opts) }
1465
1466 #define NAND_ECC_INFO(_strength, _step) \
1467 { .strength_ds = (_strength), .step_ds = (_step) }
1468 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1469 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1470
1471 /**
1472 * struct nand_flash_dev - NAND Flash Device ID Structure
1473 * @name: a human-readable name of the NAND chip
1474 * @dev_id: the device ID (the second byte of the full chip ID array)
1475 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1476 * memory address as @id[0])
1477 * @dev_id: device ID part of the full chip ID array (refers the same memory
1478 * address as @id[1])
1479 * @id: full device ID array
1480 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1481 * well as the eraseblock size) is determined from the extended NAND
1482 * chip ID array)
1483 * @chipsize: total chip size in MiB
1484 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1485 * @options: stores various chip bit options
1486 * @id_len: The valid length of the @id.
1487 * @oobsize: OOB size
1488 * @ecc: ECC correctability and step information from the datasheet.
1489 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1490 * @ecc_strength_ds in nand_chip{}.
1491 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1492 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1493 * For example, the "4bit ECC for each 512Byte" can be set with
1494 * NAND_ECC_INFO(4, 512).
1495 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1496 * reset. Should be deduced from timings described
1497 * in the datasheet.
1498 *
1499 */
1500 struct nand_flash_dev {
1501 char *name;
1502 union {
1503 struct {
1504 uint8_t mfr_id;
1505 uint8_t dev_id;
1506 };
1507 uint8_t id[NAND_MAX_ID_LEN];
1508 };
1509 unsigned int pagesize;
1510 unsigned int chipsize;
1511 unsigned int erasesize;
1512 unsigned int options;
1513 uint16_t id_len;
1514 uint16_t oobsize;
1515 struct {
1516 uint16_t strength_ds;
1517 uint16_t step_ds;
1518 } ecc;
1519 int onfi_timing_mode_default;
1520 };
1521
1522 /**
1523 * struct nand_manufacturer - NAND Flash Manufacturer structure
1524 * @name: Manufacturer name
1525 * @id: manufacturer ID code of device.
1526 * @ops: manufacturer operations
1527 */
1528 struct nand_manufacturer {
1529 int id;
1530 char *name;
1531 const struct nand_manufacturer_ops *ops;
1532 };
1533
1534 const struct nand_manufacturer *nand_get_manufacturer(u8 id);
1535
1536 static inline const char *
nand_manufacturer_name(const struct nand_manufacturer * manufacturer)1537 nand_manufacturer_name(const struct nand_manufacturer *manufacturer)
1538 {
1539 return manufacturer ? manufacturer->name : "Unknown";
1540 }
1541
1542 extern struct nand_flash_dev nand_flash_ids[];
1543
1544 extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops;
1545 extern const struct nand_manufacturer_ops samsung_nand_manuf_ops;
1546 extern const struct nand_manufacturer_ops hynix_nand_manuf_ops;
1547 extern const struct nand_manufacturer_ops micron_nand_manuf_ops;
1548 extern const struct nand_manufacturer_ops amd_nand_manuf_ops;
1549 extern const struct nand_manufacturer_ops macronix_nand_manuf_ops;
1550
1551 int nand_create_bbt(struct nand_chip *chip);
1552 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1553 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1554 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1555 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1556 int allowbbt);
1557
1558 /**
1559 * struct platform_nand_chip - chip level device structure
1560 * @nr_chips: max. number of chips to scan for
1561 * @chip_offset: chip number offset
1562 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1563 * @partitions: mtd partition list
1564 * @chip_delay: R/B delay value in us
1565 * @options: Option flags, e.g. 16bit buswidth
1566 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1567 * @part_probe_types: NULL-terminated array of probe types
1568 */
1569 struct platform_nand_chip {
1570 int nr_chips;
1571 int chip_offset;
1572 int nr_partitions;
1573 struct mtd_partition *partitions;
1574 int chip_delay;
1575 unsigned int options;
1576 unsigned int bbt_options;
1577 const char **part_probe_types;
1578 };
1579
1580 /* Keep gcc happy */
1581 struct platform_device;
1582
1583 /**
1584 * struct platform_nand_ctrl - controller level device structure
1585 * @probe: platform specific function to probe/setup hardware
1586 * @remove: platform specific function to remove/teardown hardware
1587 * @dev_ready: platform specific function to read ready/busy pin
1588 * @select_chip: platform specific chip select function
1589 * @cmd_ctrl: platform specific function for controlling
1590 * ALE/CLE/nCE. Also used to write command and address
1591 * @write_buf: platform specific function for write buffer
1592 * @read_buf: platform specific function for read buffer
1593 * @priv: private data to transport driver specific settings
1594 *
1595 * All fields are optional and depend on the hardware driver requirements
1596 */
1597 struct platform_nand_ctrl {
1598 int (*probe)(struct platform_device *pdev);
1599 void (*remove)(struct platform_device *pdev);
1600 int (*dev_ready)(struct mtd_info *mtd);
1601 void (*select_chip)(struct mtd_info *mtd, int chip);
1602 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1603 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1604 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1605 void *priv;
1606 };
1607
1608 /**
1609 * struct platform_nand_data - container structure for platform-specific data
1610 * @chip: chip level chip structure
1611 * @ctrl: controller level device structure
1612 */
1613 struct platform_nand_data {
1614 struct platform_nand_chip chip;
1615 struct platform_nand_ctrl ctrl;
1616 };
1617
1618 /* return the supported asynchronous timing mode. */
onfi_get_async_timing_mode(struct nand_chip * chip)1619 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1620 {
1621 if (!chip->parameters.onfi)
1622 return ONFI_TIMING_MODE_UNKNOWN;
1623
1624 return chip->parameters.onfi->async_timing_mode;
1625 }
1626
1627 int onfi_fill_data_interface(struct nand_chip *chip,
1628 enum nand_data_interface_type type,
1629 int timing_mode);
1630
1631 /*
1632 * Check if it is a SLC nand.
1633 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1634 * We do not distinguish the MLC and TLC now.
1635 */
nand_is_slc(struct nand_chip * chip)1636 static inline bool nand_is_slc(struct nand_chip *chip)
1637 {
1638 WARN(chip->bits_per_cell == 0,
1639 "chip->bits_per_cell is used uninitialized\n");
1640 return chip->bits_per_cell == 1;
1641 }
1642
1643 /**
1644 * Check if the opcode's address should be sent only on the lower 8 bits
1645 * @command: opcode to check
1646 */
nand_opcode_8bits(unsigned int command)1647 static inline int nand_opcode_8bits(unsigned int command)
1648 {
1649 switch (command) {
1650 case NAND_CMD_READID:
1651 case NAND_CMD_PARAM:
1652 case NAND_CMD_GET_FEATURES:
1653 case NAND_CMD_SET_FEATURES:
1654 return 1;
1655 default:
1656 break;
1657 }
1658 return 0;
1659 }
1660
1661 /* get timing characteristics from ONFI timing mode. */
1662 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1663
1664 int nand_check_erased_ecc_chunk(void *data, int datalen,
1665 void *ecc, int ecclen,
1666 void *extraoob, int extraooblen,
1667 int threshold);
1668
1669 int nand_ecc_choose_conf(struct nand_chip *chip,
1670 const struct nand_ecc_caps *caps, int oobavail);
1671
1672 /* Default write_oob implementation */
1673 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1674
1675 /* Default write_oob syndrome implementation */
1676 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1677 int page);
1678
1679 /* Default read_oob implementation */
1680 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1681
1682 /* Default read_oob syndrome implementation */
1683 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1684 int page);
1685
1686 /* Wrapper to use in order for controllers/vendors to GET/SET FEATURES */
1687 int nand_get_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
1688 int nand_set_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
1689 /* Stub used by drivers that do not support GET/SET FEATURES operations */
1690 int nand_get_set_features_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
1691 int addr, u8 *subfeature_param);
1692
1693 /* Default read_page_raw implementation */
1694 int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1695 uint8_t *buf, int oob_required, int page);
1696 int nand_read_page_raw_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
1697 u8 *buf, int oob_required, int page);
1698
1699 /* Default write_page_raw implementation */
1700 int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1701 const uint8_t *buf, int oob_required, int page);
1702 int nand_write_page_raw_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
1703 const u8 *buf, int oob_required, int page);
1704
1705 /* Reset and initialize a NAND device */
1706 int nand_reset(struct nand_chip *chip, int chipnr);
1707
1708 /* NAND operation helpers */
1709 int nand_reset_op(struct nand_chip *chip);
1710 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1711 unsigned int len);
1712 int nand_status_op(struct nand_chip *chip, u8 *status);
1713 int nand_exit_status_op(struct nand_chip *chip);
1714 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1715 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1716 unsigned int offset_in_page, void *buf, unsigned int len);
1717 int nand_change_read_column_op(struct nand_chip *chip,
1718 unsigned int offset_in_page, void *buf,
1719 unsigned int len, bool force_8bit);
1720 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1721 unsigned int offset_in_page, void *buf, unsigned int len);
1722 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1723 unsigned int offset_in_page, const void *buf,
1724 unsigned int len);
1725 int nand_prog_page_end_op(struct nand_chip *chip);
1726 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1727 unsigned int offset_in_page, const void *buf,
1728 unsigned int len);
1729 int nand_change_write_column_op(struct nand_chip *chip,
1730 unsigned int offset_in_page, const void *buf,
1731 unsigned int len, bool force_8bit);
1732 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1733 bool force_8bit);
1734 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1735 unsigned int len, bool force_8bit);
1736
1737 /*
1738 * Free resources held by the NAND device, must be called on error after a
1739 * sucessful nand_scan().
1740 */
1741 void nand_cleanup(struct nand_chip *chip);
1742 /* Unregister the MTD device and calls nand_cleanup() */
1743 void nand_release(struct mtd_info *mtd);
1744
1745 /* Default extended ID decoding function */
1746 void nand_decode_ext_id(struct nand_chip *chip);
1747
1748 /*
1749 * External helper for controller drivers that have to implement the WAITRDY
1750 * instruction and have no physical pin to check it.
1751 */
1752 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
1753
1754 #endif /* __LINUX_MTD_RAWNAND_H */
1755
