Searched refs:NUM_LINK_LEVELS (Results 1 – 3 of 3) sorted by relevance
44 #define NUM_LINK_LEVELS 2 macro53 #define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)236 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */237 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */238 …uint8_t LclkDid[NUM_LINK_LEVELS]; /* Leave at 0 to use hardcoded values in FW */
46 #define NUM_LINK_LEVELS 2 macro59 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1)340 uint8_t PcieGenSpeed[NUM_LINK_LEVELS];341 uint8_t PcieLaneCount[NUM_LINK_LEVELS];342 uint16_t LclkFreq[NUM_LINK_LEVELS];
1227 for (i = 0; i < NUM_LINK_LEVELS; i++) { in vega10_setup_default_pcie_table()1249 pcie_table->count = NUM_LINK_LEVELS; in vega10_setup_default_pcie_table()1489 while (i < NUM_LINK_LEVELS) { in vega10_populate_smc_link_levels()
