1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 #ifndef _MVPP2_H_ 10 #define _MVPP2_H_ 11 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/phy.h> 16 #include <linux/phylink.h> 17 18 /* Fifo Registers */ 19 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) 20 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) 21 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 22 #define MVPP2_RX_FIFO_INIT_REG 0x64 23 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port)) 24 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) 25 26 /* RX DMA Top Registers */ 27 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) 28 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) 29 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) 30 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) 31 #define MVPP2_POOL_BUF_SIZE_OFFSET 5 32 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) 33 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff 34 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) 35 #define MVPP2_RXQ_POOL_SHORT_OFFS 20 36 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000 37 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000 38 #define MVPP2_RXQ_POOL_LONG_OFFS 24 39 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000 40 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000 41 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 42 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 43 #define MVPP2_RXQ_DISABLE_MASK BIT(31) 44 45 /* Top Registers */ 46 #define MVPP2_MH_REG(port) (0x5040 + 4 * (port)) 47 #define MVPP2_DSA_EXTENDED BIT(5) 48 49 /* Parser Registers */ 50 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000 51 #define MVPP2_PRS_PORT_LU_MAX 0xf 52 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) 53 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) 54 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) 55 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) 56 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) 57 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) 58 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) 59 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) 60 #define MVPP2_PRS_TCAM_IDX_REG 0x1100 61 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4) 62 #define MVPP2_PRS_TCAM_INV_MASK BIT(31) 63 #define MVPP2_PRS_SRAM_IDX_REG 0x1200 64 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) 65 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230 66 #define MVPP2_PRS_TCAM_EN_MASK BIT(0) 67 #define MVPP2_PRS_TCAM_HIT_IDX_REG 0x1240 68 #define MVPP2_PRS_TCAM_HIT_CNT_REG 0x1244 69 #define MVPP2_PRS_TCAM_HIT_CNT_MASK GENMASK(15, 0) 70 71 /* RSS Registers */ 72 #define MVPP22_RSS_INDEX 0x1500 73 #define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) (idx) 74 #define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8) 75 #define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16) 76 #define MVPP22_RXQ2RSS_TABLE 0x1504 77 #define MVPP22_RSS_TABLE_POINTER(p) (p) 78 #define MVPP22_RSS_TABLE_ENTRY 0x1508 79 #define MVPP22_RSS_WIDTH 0x150c 80 81 /* Classifier Registers */ 82 #define MVPP2_CLS_MODE_REG 0x1800 83 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) 84 #define MVPP2_CLS_PORT_WAY_REG 0x1810 85 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) 86 #define MVPP2_CLS_LKP_INDEX_REG 0x1814 87 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6 88 #define MVPP2_CLS_LKP_TBL_REG 0x1818 89 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff 90 #define MVPP2_CLS_LKP_FLOW_PTR(flow) ((flow) << 16) 91 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) 92 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820 93 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824 94 #define MVPP2_CLS_FLOW_TBL0_LAST BIT(0) 95 #define MVPP2_CLS_FLOW_TBL0_ENG_MASK 0x7 96 #define MVPP2_CLS_FLOW_TBL0_OFFS 1 97 #define MVPP2_CLS_FLOW_TBL0_ENG(x) ((x) << 1) 98 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_MASK 0xff 99 #define MVPP2_CLS_FLOW_TBL0_PORT_ID(port) ((port) << 4) 100 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_SEL BIT(23) 101 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828 102 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK 0x7 103 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS(x) (x) 104 #define MVPP2_CLS_FLOW_TBL1_PRIO_MASK 0x3f 105 #define MVPP2_CLS_FLOW_TBL1_PRIO(x) ((x) << 9) 106 #define MVPP2_CLS_FLOW_TBL1_SEQ_MASK 0x7 107 #define MVPP2_CLS_FLOW_TBL1_SEQ(x) ((x) << 15) 108 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c 109 #define MVPP2_CLS_FLOW_TBL2_FLD_MASK 0x3f 110 #define MVPP2_CLS_FLOW_TBL2_FLD_OFFS(n) ((n) * 6) 111 #define MVPP2_CLS_FLOW_TBL2_FLD(n, x) ((x) << ((n) * 6)) 112 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) 113 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3 114 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7 115 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) 116 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 117 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) 118 119 /* Classifier C2 engine Registers */ 120 #define MVPP22_CLS_C2_TCAM_IDX 0x1b00 121 #define MVPP22_CLS_C2_TCAM_DATA0 0x1b10 122 #define MVPP22_CLS_C2_TCAM_DATA1 0x1b14 123 #define MVPP22_CLS_C2_TCAM_DATA2 0x1b18 124 #define MVPP22_CLS_C2_TCAM_DATA3 0x1b1c 125 #define MVPP22_CLS_C2_TCAM_DATA4 0x1b20 126 #define MVPP22_CLS_C2_PORT_ID(port) ((port) << 8) 127 #define MVPP22_CLS_C2_HIT_CTR 0x1b50 128 #define MVPP22_CLS_C2_ACT 0x1b60 129 #define MVPP22_CLS_C2_ACT_RSS_EN(act) (((act) & 0x3) << 19) 130 #define MVPP22_CLS_C2_ACT_FWD(act) (((act) & 0x7) << 13) 131 #define MVPP22_CLS_C2_ACT_QHIGH(act) (((act) & 0x3) << 11) 132 #define MVPP22_CLS_C2_ACT_QLOW(act) (((act) & 0x3) << 9) 133 #define MVPP22_CLS_C2_ATTR0 0x1b64 134 #define MVPP22_CLS_C2_ATTR0_QHIGH(qh) (((qh) & 0x1f) << 24) 135 #define MVPP22_CLS_C2_ATTR0_QHIGH_MASK 0x1f 136 #define MVPP22_CLS_C2_ATTR0_QHIGH_OFFS 24 137 #define MVPP22_CLS_C2_ATTR0_QLOW(ql) (((ql) & 0x7) << 21) 138 #define MVPP22_CLS_C2_ATTR0_QLOW_MASK 0x7 139 #define MVPP22_CLS_C2_ATTR0_QLOW_OFFS 21 140 #define MVPP22_CLS_C2_ATTR1 0x1b68 141 #define MVPP22_CLS_C2_ATTR2 0x1b6c 142 #define MVPP22_CLS_C2_ATTR2_RSS_EN BIT(30) 143 #define MVPP22_CLS_C2_ATTR3 0x1b70 144 145 /* Descriptor Manager Top Registers */ 146 #define MVPP2_RXQ_NUM_REG 0x2040 147 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044 148 #define MVPP22_DESC_ADDR_OFFS 8 149 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048 150 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 151 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) 152 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0 153 #define MVPP2_RXQ_NUM_NEW_OFFSET 16 154 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq)) 155 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff 156 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16 157 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000 158 #define MVPP2_RXQ_THRESH_REG 0x204c 159 #define MVPP2_OCCUPIED_THRESH_OFFSET 0 160 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff 161 #define MVPP2_RXQ_INDEX_REG 0x2050 162 #define MVPP2_TXQ_NUM_REG 0x2080 163 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084 164 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088 165 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0 166 #define MVPP2_TXQ_THRESH_REG 0x2094 167 #define MVPP2_TXQ_THRESH_OFFSET 16 168 #define MVPP2_TXQ_THRESH_MASK 0x3fff 169 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090 170 #define MVPP2_TXQ_INDEX_REG 0x2098 171 #define MVPP2_TXQ_PREF_BUF_REG 0x209c 172 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff) 173 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) 174 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) 175 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) 176 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) 177 #define MVPP2_TXQ_PENDING_REG 0x20a0 178 #define MVPP2_TXQ_PENDING_MASK 0x3fff 179 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4 180 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq)) 181 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16 182 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000 183 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0 184 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16 185 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4 186 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff 187 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 188 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16 189 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) 190 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8 191 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) 192 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 193 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) 194 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff 195 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu)) 196 197 /* MBUS bridge registers */ 198 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2)) 199 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2)) 200 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) 201 #define MVPP2_BASE_ADDR_ENABLE 0x4060 202 203 /* AXI Bridge Registers */ 204 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 205 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 206 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 207 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 208 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 209 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c 210 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 211 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 212 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 213 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 214 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 215 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 216 217 /* Values for AXI Bridge registers */ 218 #define MVPP22_AXI_ATTR_CACHE_OFFS 0 219 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 220 221 #define MVPP22_AXI_CODE_CACHE_OFFS 0 222 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4 223 224 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 225 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 226 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb 227 228 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 229 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 230 231 /* Interrupt Cause and Mask registers */ 232 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port)) 233 #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0 234 235 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) 236 #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0 237 #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port)) 238 239 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400 240 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf 241 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 242 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7 243 244 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf 245 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 246 247 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404 248 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f 249 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00 250 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8 251 252 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) 253 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) 254 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) 255 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) 256 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff 257 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 258 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 259 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) 260 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) 261 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) 262 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) 263 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) 264 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) 265 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) 266 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc 267 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff 268 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 269 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) 270 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 271 272 /* Buffer Manager registers */ 273 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) 274 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80 275 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) 276 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0 277 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) 278 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0 279 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) 280 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0 281 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) 282 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) 283 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff 284 #define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8 285 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) 286 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) 287 #define MVPP2_BM_START_MASK BIT(0) 288 #define MVPP2_BM_STOP_MASK BIT(1) 289 #define MVPP2_BM_STATE_MASK BIT(4) 290 #define MVPP2_BM_LOW_THRESH_OFFS 8 291 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00 292 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ 293 MVPP2_BM_LOW_THRESH_OFFS) 294 #define MVPP2_BM_HIGH_THRESH_OFFS 16 295 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 296 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ 297 MVPP2_BM_HIGH_THRESH_OFFS) 298 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) 299 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) 300 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) 301 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) 302 #define MVPP2_BM_BPPE_FULL_MASK BIT(3) 303 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) 304 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4)) 305 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) 306 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) 307 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440 308 #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444 309 #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff 310 #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00 311 #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8 312 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) 313 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) 314 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) 315 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) 316 #define MVPP2_BM_VIRT_RLS_REG 0x64c0 317 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4 318 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff 319 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 320 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 321 322 /* Hit counters registers */ 323 #define MVPP2_CTRS_IDX 0x7040 324 #define MVPP2_CLS_DEC_TBL_HIT_CTR 0x7700 325 #define MVPP2_CLS_FLOW_TBL_HIT_CTR 0x7704 326 327 /* TX Scheduler registers */ 328 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 329 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 330 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff 331 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8 332 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 333 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 334 #define MVPP2_TXP_SCHED_MTU_REG 0x801c 335 #define MVPP2_TXP_MTU_MAX 0x7FFFF 336 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020 337 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff 338 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000 339 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20) 340 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024 341 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff 342 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2)) 343 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff 344 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000 345 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20) 346 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2)) 347 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff 348 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) 349 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff 350 351 /* TX general registers */ 352 #define MVPP2_TX_SNOOP_REG 0x8800 353 #define MVPP2_TX_PORT_FLUSH_REG 0x8810 354 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) 355 356 /* LMS registers */ 357 #define MVPP2_SRC_ADDR_MIDDLE 0x24 358 #define MVPP2_SRC_ADDR_HIGH 0x28 359 #define MVPP2_PHY_AN_CFG0_REG 0x34 360 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) 361 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c 362 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 363 364 /* Per-port registers */ 365 #define MVPP2_GMAC_CTRL_0_REG 0x0 366 #define MVPP2_GMAC_PORT_EN_MASK BIT(0) 367 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) 368 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 369 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc 370 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) 371 #define MVPP2_GMAC_CTRL_1_REG 0x4 372 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) 373 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) 374 #define MVPP2_GMAC_PCS_LB_EN_BIT 6 375 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) 376 #define MVPP2_GMAC_SA_LOW_OFFS 7 377 #define MVPP2_GMAC_CTRL_2_REG 0x8 378 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) 379 #define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1) 380 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) 381 #define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4) 382 #define MVPP2_GMAC_DISABLE_PADDING BIT(5) 383 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) 384 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc 385 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) 386 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) 387 #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) 388 #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) 389 #define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4) 390 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) 391 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) 392 #define MVPP2_GMAC_AN_SPEED_EN BIT(7) 393 #define MVPP2_GMAC_FC_ADV_EN BIT(9) 394 #define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10) 395 #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11) 396 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) 397 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) 398 #define MVPP2_GMAC_STATUS0 0x10 399 #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0) 400 #define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1) 401 #define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2) 402 #define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3) 403 #define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(6) 404 #define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(7) 405 #define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11) 406 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c 407 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 408 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 409 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ 410 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) 411 #define MVPP22_GMAC_INT_STAT 0x20 412 #define MVPP22_GMAC_INT_STAT_LINK BIT(1) 413 #define MVPP22_GMAC_INT_MASK 0x24 414 #define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1) 415 #define MVPP22_GMAC_CTRL_4_REG 0x90 416 #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) 417 #define MVPP22_CTRL4_RX_FC_EN BIT(3) 418 #define MVPP22_CTRL4_TX_FC_EN BIT(4) 419 #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) 420 #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) 421 #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) 422 #define MVPP22_GMAC_INT_SUM_MASK 0xa4 423 #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1) 424 425 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0, 426 * relative to port->base. 427 */ 428 #define MVPP22_XLG_CTRL0_REG 0x100 429 #define MVPP22_XLG_CTRL0_PORT_EN BIT(0) 430 #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1) 431 #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) 432 #define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8) 433 #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) 434 #define MVPP22_XLG_CTRL1_REG 0x104 435 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0 436 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff 437 #define MVPP22_XLG_STATUS 0x10c 438 #define MVPP22_XLG_STATUS_LINK_UP BIT(0) 439 #define MVPP22_XLG_INT_STAT 0x114 440 #define MVPP22_XLG_INT_STAT_LINK BIT(1) 441 #define MVPP22_XLG_INT_MASK 0x118 442 #define MVPP22_XLG_INT_MASK_LINK BIT(1) 443 #define MVPP22_XLG_CTRL3_REG 0x11c 444 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) 445 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) 446 #define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13) 447 #define MVPP22_XLG_EXT_INT_MASK 0x15c 448 #define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1) 449 #define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2) 450 #define MVPP22_XLG_CTRL4_REG 0x184 451 #define MVPP22_XLG_CTRL4_FWD_FC BIT(5) 452 #define MVPP22_XLG_CTRL4_FWD_PFC BIT(6) 453 #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12) 454 #define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14) 455 456 /* SMI registers. PPv2.2 only, relative to priv->iface_base. */ 457 #define MVPP22_SMI_MISC_CFG_REG 0x1204 458 #define MVPP22_SMI_POLLING_EN BIT(10) 459 460 #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00) 461 462 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 463 464 /* Descriptor ring Macros */ 465 #define MVPP2_QUEUE_NEXT_DESC(q, index) \ 466 (((index) < (q)->last_desc) ? ((index) + 1) : 0) 467 468 /* XPCS registers. PPv2.2 only */ 469 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000) 470 #define MVPP22_MPCS_CTRL 0x14 471 #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10) 472 #define MVPP22_MPCS_CLK_RESET 0x14c 473 #define MAC_CLK_RESET_SD_TX BIT(0) 474 #define MAC_CLK_RESET_SD_RX BIT(1) 475 #define MAC_CLK_RESET_MAC BIT(2) 476 #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4) 477 #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) 478 479 /* XPCS registers. PPv2.2 only */ 480 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) 481 #define MVPP22_XPCS_CFG0 0x0 482 #define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3) 483 #define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5) 484 485 /* System controller registers. Accessed through a regmap. */ 486 #define GENCONF_SOFT_RESET1 0x1108 487 #define GENCONF_SOFT_RESET1_GOP BIT(6) 488 #define GENCONF_PORT_CTRL0 0x1110 489 #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1) 490 #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29) 491 #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) 492 #define GENCONF_PORT_CTRL1 0x1114 493 #define GENCONF_PORT_CTRL1_EN(p) BIT(p) 494 #define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28) 495 #define GENCONF_CTRL0 0x1120 496 #define GENCONF_CTRL0_PORT0_RGMII BIT(0) 497 #define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1) 498 #define GENCONF_CTRL0_PORT1_RGMII BIT(2) 499 500 /* Various constants */ 501 502 /* Coalescing */ 503 #define MVPP2_TXDONE_COAL_PKTS_THRESH 64 504 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL 505 #define MVPP2_TXDONE_COAL_USEC 1000 506 #define MVPP2_RX_COAL_PKTS 32 507 #define MVPP2_RX_COAL_USEC 64 508 509 /* The two bytes Marvell header. Either contains a special value used 510 * by Marvell switches when a specific hardware mode is enabled (not 511 * supported by this driver) or is filled automatically by zeroes on 512 * the RX side. Those two bytes being at the front of the Ethernet 513 * header, they allow to have the IP header aligned on a 4 bytes 514 * boundary automatically: the hardware skips those two bytes on its 515 * own. 516 */ 517 #define MVPP2_MH_SIZE 2 518 #define MVPP2_ETH_TYPE_LEN 2 519 #define MVPP2_PPPOE_HDR_SIZE 8 520 #define MVPP2_VLAN_TAG_LEN 4 521 #define MVPP2_VLAN_TAG_EDSA_LEN 8 522 523 /* Lbtd 802.3 type */ 524 #define MVPP2_IP_LBDT_TYPE 0xfffa 525 526 #define MVPP2_TX_CSUM_MAX_SIZE 9800 527 528 /* Timeout constants */ 529 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000 530 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000 531 532 #define MVPP2_TX_MTU_MAX 0x7ffff 533 534 /* Maximum number of T-CONTs of PON port */ 535 #define MVPP2_MAX_TCONT 16 536 537 /* Maximum number of supported ports */ 538 #define MVPP2_MAX_PORTS 4 539 540 /* Maximum number of TXQs used by single port */ 541 #define MVPP2_MAX_TXQ 8 542 543 /* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO 544 * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data), 545 * multiply this value by two to count the maximum number of skb descs needed. 546 */ 547 #define MVPP2_MAX_TSO_SEGS 300 548 #define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 549 550 /* Dfault number of RXQs in use */ 551 #define MVPP2_DEFAULT_RXQ 1 552 553 /* Max number of Rx descriptors */ 554 #define MVPP2_MAX_RXD_MAX 1024 555 #define MVPP2_MAX_RXD_DFLT 128 556 557 /* Max number of Tx descriptors */ 558 #define MVPP2_MAX_TXD_MAX 2048 559 #define MVPP2_MAX_TXD_DFLT 1024 560 561 /* Amount of Tx descriptors that can be reserved at once by CPU */ 562 #define MVPP2_CPU_DESC_CHUNK 64 563 564 /* Max number of Tx descriptors in each aggregated queue */ 565 #define MVPP2_AGGR_TXQ_SIZE 256 566 567 /* Descriptor aligned size */ 568 #define MVPP2_DESC_ALIGNED_SIZE 32 569 570 /* Descriptor alignment mask */ 571 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) 572 573 /* RX FIFO constants */ 574 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000 575 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000 576 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000 577 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200 578 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80 579 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40 580 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 581 582 /* TX FIFO constants */ 583 #define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa 584 #define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3 585 #define MVPP2_TX_FIFO_THRESHOLD_MIN 256 586 #define MVPP2_TX_FIFO_THRESHOLD_10KB \ 587 (MVPP22_TX_FIFO_DATA_SIZE_10KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 588 #define MVPP2_TX_FIFO_THRESHOLD_3KB \ 589 (MVPP22_TX_FIFO_DATA_SIZE_3KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 590 591 /* RX buffer constants */ 592 #define MVPP2_SKB_SHINFO_SIZE \ 593 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 594 595 #define MVPP2_RX_PKT_SIZE(mtu) \ 596 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \ 597 ETH_HLEN + ETH_FCS_LEN, cache_line_size()) 598 599 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) 600 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE) 601 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \ 602 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE) 603 604 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) 605 #define MVPP2_BIT_TO_WORD(bit) ((bit) / 32) 606 #define MVPP2_BIT_IN_WORD(bit) ((bit) % 32) 607 608 /* RSS constants */ 609 #define MVPP22_RSS_TABLE_ENTRIES 32 610 611 /* IPv6 max L3 address size */ 612 #define MVPP2_MAX_L3_ADDR_SIZE 16 613 614 /* Port flags */ 615 #define MVPP2_F_LOOPBACK BIT(0) 616 617 /* Marvell tag types */ 618 enum mvpp2_tag_type { 619 MVPP2_TAG_TYPE_NONE = 0, 620 MVPP2_TAG_TYPE_MH = 1, 621 MVPP2_TAG_TYPE_DSA = 2, 622 MVPP2_TAG_TYPE_EDSA = 3, 623 MVPP2_TAG_TYPE_VLAN = 4, 624 MVPP2_TAG_TYPE_LAST = 5 625 }; 626 627 /* L2 cast enum */ 628 enum mvpp2_prs_l2_cast { 629 MVPP2_PRS_L2_UNI_CAST, 630 MVPP2_PRS_L2_MULTI_CAST, 631 }; 632 633 /* L3 cast enum */ 634 enum mvpp2_prs_l3_cast { 635 MVPP2_PRS_L3_UNI_CAST, 636 MVPP2_PRS_L3_MULTI_CAST, 637 MVPP2_PRS_L3_BROAD_CAST 638 }; 639 640 /* BM constants */ 641 #define MVPP2_BM_JUMBO_BUF_NUM 512 642 #define MVPP2_BM_LONG_BUF_NUM 1024 643 #define MVPP2_BM_SHORT_BUF_NUM 2048 644 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) 645 #define MVPP2_BM_POOL_PTR_ALIGN 128 646 647 /* BM cookie (32 bits) definition */ 648 #define MVPP2_BM_COOKIE_POOL_OFFS 8 649 #define MVPP2_BM_COOKIE_CPU_OFFS 24 650 651 #define MVPP2_BM_SHORT_FRAME_SIZE 512 652 #define MVPP2_BM_LONG_FRAME_SIZE 2048 653 #define MVPP2_BM_JUMBO_FRAME_SIZE 10240 654 /* BM short pool packet size 655 * These value assure that for SWF the total number 656 * of bytes allocated for each buffer will be 512 657 */ 658 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_SHORT_FRAME_SIZE) 659 #define MVPP2_BM_LONG_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_LONG_FRAME_SIZE) 660 #define MVPP2_BM_JUMBO_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_JUMBO_FRAME_SIZE) 661 662 #define MVPP21_ADDR_SPACE_SZ 0 663 #define MVPP22_ADDR_SPACE_SZ SZ_64K 664 665 #define MVPP2_MAX_THREADS 8 666 #define MVPP2_MAX_QVECS MVPP2_MAX_THREADS 667 668 /* GMAC MIB Counters register definitions */ 669 #define MVPP21_MIB_COUNTERS_OFFSET 0x1000 670 #define MVPP21_MIB_COUNTERS_PORT_SZ 0x400 671 #define MVPP22_MIB_COUNTERS_OFFSET 0x0 672 #define MVPP22_MIB_COUNTERS_PORT_SZ 0x100 673 674 #define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0 675 #define MVPP2_MIB_BAD_OCTETS_RCVD 0x8 676 #define MVPP2_MIB_CRC_ERRORS_SENT 0xc 677 #define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10 678 #define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18 679 #define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c 680 #define MVPP2_MIB_FRAMES_64_OCTETS 0x20 681 #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24 682 #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28 683 #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c 684 #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30 685 #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 686 #define MVPP2_MIB_GOOD_OCTETS_SENT 0x38 687 #define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40 688 #define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48 689 #define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c 690 #define MVPP2_MIB_FC_SENT 0x54 691 #define MVPP2_MIB_FC_RCVD 0x58 692 #define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c 693 #define MVPP2_MIB_UNDERSIZE_RCVD 0x60 694 #define MVPP2_MIB_FRAGMENTS_RCVD 0x64 695 #define MVPP2_MIB_OVERSIZE_RCVD 0x68 696 #define MVPP2_MIB_JABBER_RCVD 0x6c 697 #define MVPP2_MIB_MAC_RCV_ERROR 0x70 698 #define MVPP2_MIB_BAD_CRC_EVENT 0x74 699 #define MVPP2_MIB_COLLISION 0x78 700 #define MVPP2_MIB_LATE_COLLISION 0x7c 701 702 #define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ) 703 704 #define MVPP2_DESC_DMA_MASK DMA_BIT_MASK(40) 705 706 /* Definitions */ 707 708 /* Shared Packet Processor resources */ 709 struct mvpp2 { 710 /* Shared registers' base addresses */ 711 void __iomem *lms_base; 712 void __iomem *iface_base; 713 714 /* On PPv2.2, each "software thread" can access the base 715 * register through a separate address space, each 64 KB apart 716 * from each other. Typically, such address spaces will be 717 * used per CPU. 718 */ 719 void __iomem *swth_base[MVPP2_MAX_THREADS]; 720 721 /* On PPv2.2, some port control registers are located into the system 722 * controller space. These registers are accessible through a regmap. 723 */ 724 struct regmap *sysctrl_base; 725 726 /* Common clocks */ 727 struct clk *pp_clk; 728 struct clk *gop_clk; 729 struct clk *mg_clk; 730 struct clk *mg_core_clk; 731 struct clk *axi_clk; 732 733 /* List of pointers to port structures */ 734 int port_count; 735 struct mvpp2_port *port_list[MVPP2_MAX_PORTS]; 736 737 /* Aggregated TXQs */ 738 struct mvpp2_tx_queue *aggr_txqs; 739 740 /* BM pools */ 741 struct mvpp2_bm_pool *bm_pools; 742 743 /* PRS shadow table */ 744 struct mvpp2_prs_shadow *prs_shadow; 745 /* PRS auxiliary table for double vlan entries control */ 746 bool *prs_double_vlans; 747 748 /* Tclk value */ 749 u32 tclk; 750 751 /* HW version */ 752 enum { MVPP21, MVPP22 } hw_version; 753 754 /* Maximum number of RXQs per port */ 755 unsigned int max_port_rxqs; 756 757 /* Workqueue to gather hardware statistics */ 758 char queue_name[30]; 759 struct workqueue_struct *stats_queue; 760 761 /* Debugfs root entry */ 762 struct dentry *dbgfs_dir; 763 }; 764 765 struct mvpp2_pcpu_stats { 766 struct u64_stats_sync syncp; 767 u64 rx_packets; 768 u64 rx_bytes; 769 u64 tx_packets; 770 u64 tx_bytes; 771 }; 772 773 /* Per-CPU port control */ 774 struct mvpp2_port_pcpu { 775 struct hrtimer tx_done_timer; 776 bool timer_scheduled; 777 /* Tasklet for egress finalization */ 778 struct tasklet_struct tx_done_tasklet; 779 }; 780 781 struct mvpp2_queue_vector { 782 int irq; 783 struct napi_struct napi; 784 enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type; 785 int sw_thread_id; 786 u16 sw_thread_mask; 787 int first_rxq; 788 int nrxqs; 789 u32 pending_cause_rx; 790 struct mvpp2_port *port; 791 }; 792 793 struct mvpp2_port { 794 u8 id; 795 796 /* Index of the port from the "group of ports" complex point 797 * of view 798 */ 799 int gop_id; 800 801 int link_irq; 802 803 struct mvpp2 *priv; 804 805 /* Firmware node associated to the port */ 806 struct fwnode_handle *fwnode; 807 808 /* Is a PHY always connected to the port */ 809 bool has_phy; 810 811 /* Per-port registers' base address */ 812 void __iomem *base; 813 void __iomem *stats_base; 814 815 struct mvpp2_rx_queue **rxqs; 816 unsigned int nrxqs; 817 struct mvpp2_tx_queue **txqs; 818 unsigned int ntxqs; 819 struct net_device *dev; 820 821 int pkt_size; 822 823 /* Per-CPU port control */ 824 struct mvpp2_port_pcpu __percpu *pcpu; 825 826 /* Flags */ 827 unsigned long flags; 828 829 u16 tx_ring_size; 830 u16 rx_ring_size; 831 struct mvpp2_pcpu_stats __percpu *stats; 832 u64 *ethtool_stats; 833 834 /* Per-port work and its lock to gather hardware statistics */ 835 struct mutex gather_stats_lock; 836 struct delayed_work stats_work; 837 838 struct device_node *of_node; 839 840 phy_interface_t phy_interface; 841 struct phylink *phylink; 842 struct phy *comphy; 843 844 struct mvpp2_bm_pool *pool_long; 845 struct mvpp2_bm_pool *pool_short; 846 847 /* Index of first port's physical RXQ */ 848 u8 first_rxq; 849 850 struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS]; 851 unsigned int nqvecs; 852 bool has_tx_irqs; 853 854 u32 tx_time_coal; 855 856 /* RSS indirection table */ 857 u32 indir[MVPP22_RSS_TABLE_ENTRIES]; 858 }; 859 860 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the 861 * layout of the transmit and reception DMA descriptors, and their 862 * layout is therefore defined by the hardware design 863 */ 864 865 #define MVPP2_TXD_L3_OFF_SHIFT 0 866 #define MVPP2_TXD_IP_HLEN_SHIFT 8 867 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13) 868 #define MVPP2_TXD_L4_CSUM_NOT BIT(14) 869 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) 870 #define MVPP2_TXD_PADDING_DISABLE BIT(23) 871 #define MVPP2_TXD_L4_UDP BIT(24) 872 #define MVPP2_TXD_L3_IP6 BIT(26) 873 #define MVPP2_TXD_L_DESC BIT(28) 874 #define MVPP2_TXD_F_DESC BIT(29) 875 876 #define MVPP2_RXD_ERR_SUMMARY BIT(15) 877 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) 878 #define MVPP2_RXD_ERR_CRC 0x0 879 #define MVPP2_RXD_ERR_OVERRUN BIT(13) 880 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) 881 #define MVPP2_RXD_BM_POOL_ID_OFFS 16 882 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) 883 #define MVPP2_RXD_HWF_SYNC BIT(21) 884 #define MVPP2_RXD_L4_CSUM_OK BIT(22) 885 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24) 886 #define MVPP2_RXD_L4_TCP BIT(25) 887 #define MVPP2_RXD_L4_UDP BIT(26) 888 #define MVPP2_RXD_L3_IP4 BIT(28) 889 #define MVPP2_RXD_L3_IP6 BIT(30) 890 #define MVPP2_RXD_BUF_HDR BIT(31) 891 892 /* HW TX descriptor for PPv2.1 */ 893 struct mvpp21_tx_desc { 894 __le32 command; /* Options used by HW for packet transmitting.*/ 895 u8 packet_offset; /* the offset from the buffer beginning */ 896 u8 phys_txq; /* destination queue ID */ 897 __le16 data_size; /* data size of transmitted packet in bytes */ 898 __le32 buf_dma_addr; /* physical addr of transmitted buffer */ 899 __le32 buf_cookie; /* cookie for access to TX buffer in tx path */ 900 __le32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */ 901 __le32 reserved2; /* reserved (for future use) */ 902 }; 903 904 /* HW RX descriptor for PPv2.1 */ 905 struct mvpp21_rx_desc { 906 __le32 status; /* info about received packet */ 907 __le16 reserved1; /* parser_info (for future use, PnC) */ 908 __le16 data_size; /* size of received packet in bytes */ 909 __le32 buf_dma_addr; /* physical address of the buffer */ 910 __le32 buf_cookie; /* cookie for access to RX buffer in rx path */ 911 __le16 reserved2; /* gem_port_id (for future use, PON) */ 912 __le16 reserved3; /* csum_l4 (for future use, PnC) */ 913 u8 reserved4; /* bm_qset (for future use, BM) */ 914 u8 reserved5; 915 __le16 reserved6; /* classify_info (for future use, PnC) */ 916 __le32 reserved7; /* flow_id (for future use, PnC) */ 917 __le32 reserved8; 918 }; 919 920 /* HW TX descriptor for PPv2.2 */ 921 struct mvpp22_tx_desc { 922 __le32 command; 923 u8 packet_offset; 924 u8 phys_txq; 925 __le16 data_size; 926 __le64 reserved1; 927 __le64 buf_dma_addr_ptp; 928 __le64 buf_cookie_misc; 929 }; 930 931 /* HW RX descriptor for PPv2.2 */ 932 struct mvpp22_rx_desc { 933 __le32 status; 934 __le16 reserved1; 935 __le16 data_size; 936 __le32 reserved2; 937 __le32 reserved3; 938 __le64 buf_dma_addr_key_hash; 939 __le64 buf_cookie_misc; 940 }; 941 942 /* Opaque type used by the driver to manipulate the HW TX and RX 943 * descriptors 944 */ 945 struct mvpp2_tx_desc { 946 union { 947 struct mvpp21_tx_desc pp21; 948 struct mvpp22_tx_desc pp22; 949 }; 950 }; 951 952 struct mvpp2_rx_desc { 953 union { 954 struct mvpp21_rx_desc pp21; 955 struct mvpp22_rx_desc pp22; 956 }; 957 }; 958 959 struct mvpp2_txq_pcpu_buf { 960 /* Transmitted SKB */ 961 struct sk_buff *skb; 962 963 /* Physical address of transmitted buffer */ 964 dma_addr_t dma; 965 966 /* Size transmitted */ 967 size_t size; 968 }; 969 970 /* Per-CPU Tx queue control */ 971 struct mvpp2_txq_pcpu { 972 int cpu; 973 974 /* Number of Tx DMA descriptors in the descriptor ring */ 975 int size; 976 977 /* Number of currently used Tx DMA descriptor in the 978 * descriptor ring 979 */ 980 int count; 981 982 int wake_threshold; 983 int stop_threshold; 984 985 /* Number of Tx DMA descriptors reserved for each CPU */ 986 int reserved_num; 987 988 /* Infos about transmitted buffers */ 989 struct mvpp2_txq_pcpu_buf *buffs; 990 991 /* Index of last TX DMA descriptor that was inserted */ 992 int txq_put_index; 993 994 /* Index of the TX DMA descriptor to be cleaned up */ 995 int txq_get_index; 996 997 /* DMA buffer for TSO headers */ 998 char *tso_headers; 999 dma_addr_t tso_headers_dma; 1000 }; 1001 1002 struct mvpp2_tx_queue { 1003 /* Physical number of this Tx queue */ 1004 u8 id; 1005 1006 /* Logical number of this Tx queue */ 1007 u8 log_id; 1008 1009 /* Number of Tx DMA descriptors in the descriptor ring */ 1010 int size; 1011 1012 /* Number of currently used Tx DMA descriptor in the descriptor ring */ 1013 int count; 1014 1015 /* Per-CPU control of physical Tx queues */ 1016 struct mvpp2_txq_pcpu __percpu *pcpu; 1017 1018 u32 done_pkts_coal; 1019 1020 /* Virtual address of thex Tx DMA descriptors array */ 1021 struct mvpp2_tx_desc *descs; 1022 1023 /* DMA address of the Tx DMA descriptors array */ 1024 dma_addr_t descs_dma; 1025 1026 /* Index of the last Tx DMA descriptor */ 1027 int last_desc; 1028 1029 /* Index of the next Tx DMA descriptor to process */ 1030 int next_desc_to_proc; 1031 }; 1032 1033 struct mvpp2_rx_queue { 1034 /* RX queue number, in the range 0-31 for physical RXQs */ 1035 u8 id; 1036 1037 /* Num of rx descriptors in the rx descriptor ring */ 1038 int size; 1039 1040 u32 pkts_coal; 1041 u32 time_coal; 1042 1043 /* Virtual address of the RX DMA descriptors array */ 1044 struct mvpp2_rx_desc *descs; 1045 1046 /* DMA address of the RX DMA descriptors array */ 1047 dma_addr_t descs_dma; 1048 1049 /* Index of the last RX DMA descriptor */ 1050 int last_desc; 1051 1052 /* Index of the next RX DMA descriptor to process */ 1053 int next_desc_to_proc; 1054 1055 /* ID of port to which physical RXQ is mapped */ 1056 int port; 1057 1058 /* Port's logic RXQ number to which physical RXQ is mapped */ 1059 int logic_rxq; 1060 }; 1061 1062 struct mvpp2_bm_pool { 1063 /* Pool number in the range 0-7 */ 1064 int id; 1065 1066 /* Buffer Pointers Pool External (BPPE) size */ 1067 int size; 1068 /* BPPE size in bytes */ 1069 int size_bytes; 1070 /* Number of buffers for this pool */ 1071 int buf_num; 1072 /* Pool buffer size */ 1073 int buf_size; 1074 /* Packet size */ 1075 int pkt_size; 1076 int frag_size; 1077 1078 /* BPPE virtual base address */ 1079 u32 *virt_addr; 1080 /* BPPE DMA base address */ 1081 dma_addr_t dma_addr; 1082 1083 /* Ports using BM pool */ 1084 u32 port_map; 1085 }; 1086 1087 #define IS_TSO_HEADER(txq_pcpu, addr) \ 1088 ((addr) >= (txq_pcpu)->tso_headers_dma && \ 1089 (addr) < (txq_pcpu)->tso_headers_dma + \ 1090 (txq_pcpu)->size * TSO_HEADER_SIZE) 1091 1092 #define MVPP2_DRIVER_NAME "mvpp2" 1093 #define MVPP2_DRIVER_VERSION "1.0" 1094 1095 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data); 1096 u32 mvpp2_read(struct mvpp2 *priv, u32 offset); 1097 1098 u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset); 1099 1100 void mvpp2_percpu_write(struct mvpp2 *priv, int cpu, u32 offset, u32 data); 1101 u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu, u32 offset); 1102 1103 void mvpp2_percpu_write_relaxed(struct mvpp2 *priv, int cpu, u32 offset, 1104 u32 data); 1105 1106 void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name); 1107 1108 void mvpp2_dbgfs_cleanup(struct mvpp2 *priv); 1109 1110 #endif 1111
