Searched refs:MVPP22_XLG_CTRL0_REG (Results 1 – 2 of 2) sorted by relevance
1181 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()1185 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()1202 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()1204 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()1208 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()4313 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp22_xlg_link_state()4394 ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_config()4406 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_config()
428 #define MVPP22_XLG_CTRL0_REG 0x100 macro
