MUX_MODE1 (reference) in projects: Linux-v4.19

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Searched refs:MUX_MODE1 (Results 1 – 25 of 61) sorted by relevance

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/Linux-v4.19/arch/arm/boot/dts/
D	dra72x-mmc-iodelay.dtsi	133 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a23.mmc2_clk / 134 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_cs1.mmc2_cmd / 135 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a24.mmc2_dat0 / 136 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a25.mmc2_dat1 / 137 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a26.mmc2_dat2 / 138 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a27.mmc2_dat3 / 139 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a19.mmc2_dat4 / 140 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a20.mmc2_dat5 / 141 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a21.mmc2_dat6 / 142 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a22.mmc2_dat7 */ [all …]
D	dra74x-mmc-iodelay.dtsi	120 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a23.mmc2_clk / 121 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_cs1.mmc2_cmd / 122 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a24.mmc2_dat0 / 123 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a25.mmc2_dat1 / 124 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a26.mmc2_dat2 / 125 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a27.mmc2_dat3 / 126 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a19.mmc2_dat4 / 127 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a20.mmc2_dat5 / 128 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a21.mmc2_dat6 / 129 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a22.mmc2_dat7 */ [all …]
D	am335x-wega.dtsi	103 AM33XX_IOPAD(0x840, PIN_OUTPUT \| MUX_MODE1) /* gpmc_a0.mii2_txen / 104 AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN \| MUX_MODE1) / gpmc_a1.mii2_rxdv / 105 AM33XX_IOPAD(0x848, PIN_OUTPUT \| MUX_MODE1) / gpmc_a2.mii2_txd3 / 106 AM33XX_IOPAD(0x84c, PIN_OUTPUT \| MUX_MODE1) / gpmc_a3.mii2_txd2 / 107 AM33XX_IOPAD(0x850, PIN_OUTPUT \| MUX_MODE1) / gpmc_a4.mii2_txd1 / 108 AM33XX_IOPAD(0x854, PIN_OUTPUT \| MUX_MODE1) / gpmc_a5.mii2_txd0 / 109 AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN \| MUX_MODE1) / gpmc_a6.mii2_txclk / 110 AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN \| MUX_MODE1) / gpmc_a7.mii2_rxclk / 111 AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN \| MUX_MODE1) / gpmc_a8.mii2_rxd3 / 112 AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN \| MUX_MODE1) / gpmc_a9.mii2_rxd2 */ [all …]
D	omap4-kc1.dts	78 OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP \| MUX_MODE1) /* sdmmc2_dat0 / 79 OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP \| MUX_MODE1) / sdmmc2_dat1 / 80 OMAP4_IOPAD(0x044, PIN_INPUT_PULLUP \| MUX_MODE1) / sdmmc2_dat2 / 81 OMAP4_IOPAD(0x046, PIN_INPUT_PULLUP \| MUX_MODE1) / sdmmc2_dat3 / 82 OMAP4_IOPAD(0x048, PIN_INPUT_PULLUP \| MUX_MODE1) / sdmmc2_dat4 / 83 OMAP4_IOPAD(0x04a, PIN_INPUT_PULLUP \| MUX_MODE1) / sdmmc2_dat5 / 84 OMAP4_IOPAD(0x04c, PIN_INPUT_PULLUP \| MUX_MODE1) / sdmmc2_dat6 / 85 OMAP4_IOPAD(0x04e, PIN_INPUT_PULLUP \| MUX_MODE1) / sdmmc2_dat7 / 86 OMAP4_IOPAD(0x082, PIN_INPUT_PULLUP \| MUX_MODE1) / sdmmc2_clk / 87 OMAP4_IOPAD(0x084, PIN_INPUT_PULLUP \| MUX_MODE1) / sdmmc2_cmd */
D	am335x-lxm.dts	69 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN \| MUX_MODE1) /* rmii1_crs_dv / 70 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN \| MUX_MODE1) / rmii1_rxer / 71 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN \| MUX_MODE1) / rmii1_txen / 72 AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN \| MUX_MODE1) / rmii1_td1 / 73 AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN \| MUX_MODE1) / rmii1_td0 / 74 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN \| MUX_MODE1) / rmii1_rd1 / 75 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN \| MUX_MODE1) / rmii1_rd0 / 87 AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN \| MUX_MODE1) / rmii2_refclk / 137 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_ad0.mmc1_dat0 / 138 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_ad1.mmc1_dat1 */ [all …]
D	dra76x-mmc-iodelay.dtsi	76 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a23.mmc2_clk / 77 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_cs1.mmc2_cmd / 78 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a24.mmc2_dat0 / 79 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a25.mmc2_dat1 / 80 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a26.mmc2_dat2 / 81 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a27.mmc2_dat3 / 82 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a19.mmc2_dat4 / 83 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a20.mmc2_dat5 / 84 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a21.mmc2_dat6 / 85 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a22.mmc2_dat7 */ [all …]
D	am335x-pdu001.dts	140 AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP \| MUX_MODE1) /* spi0_cs1.uart3_rxd / 141 AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN \| MUX_MODE1) / ecap0_in_pwm0_out.uart3_txd / 171 AM33XX_IOPAD(0x840, PIN_OUTPUT \| MUX_MODE1) / mii2_txen.gpmc_a0 / 172 AM33XX_IOPAD(0x844, PIN_INPUT \| MUX_MODE1) / mii2_rxdv.gpmc_a1 / 173 AM33XX_IOPAD(0x848, PIN_OUTPUT \| MUX_MODE1) / mii2_txd3.gpmc_a2 / 174 AM33XX_IOPAD(0x84c, PIN_OUTPUT \| MUX_MODE1) / mii2_txd2.gpmc_a3 / 175 AM33XX_IOPAD(0x850, PIN_OUTPUT \| MUX_MODE1) / mii2_txd1.gpmc_a4 / 176 AM33XX_IOPAD(0x854, PIN_OUTPUT \| MUX_MODE1) / mii2_txd0.gpmc_a5 / 177 AM33XX_IOPAD(0x858, PIN_INPUT \| MUX_MODE1) / mii2_txclk.gpmc_a6 / 178 AM33XX_IOPAD(0x85c, PIN_INPUT \| MUX_MODE1) / mii2_rxclk.gpmc_a7 */ [all …]
D	omap4-var-som-om44-wlan.dtsi	`44 OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP \| MUX_MODE1) /* mcspi4_clk.sdmmc4_clk / 45 OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP \| MUX_MODE1) / mcspi4_simo.sdmmc4_cmd / 46 OMAP4_IOPAD(0x158, PIN_INPUT_PULLUP \| MUX_MODE1) / mcspi4_somi.sdmmc4_dat0 / 47 OMAP4_IOPAD(0x15e, PIN_INPUT_PULLUP \| MUX_MODE1) / uart4_tx.sdmmc4_dat1 / 48 OMAP4_IOPAD(0x15c, PIN_INPUT_PULLUP \| MUX_MODE1) / uart4_rx.sdmmc4_dat2 / 49 OMAP4_IOPAD(0x15a, PIN_INPUT_PULLUP \| MUX_MODE1) / mcspi4_cs0.sdmmc4_dat3 */`
D	keystone-k2g-evm.dts	135 K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B \| PULL_DISABLE \| MUX_MODE1) /* qspicsn2.dcan1tx / 136 K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B \| PIN_PULLDOWN \| MUX_MODE1) / qspicsn3.dcan1rx / 142 K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_RXD1.RGMII_RXD1 / 143 K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_RXD2.RGMII_RXD2 / 144 K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_RXD3.RGMII_RXD3 / 145 K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_RXD0.RGMII_RXD0 / 146 K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_TXD0.RGMII_TXD0 / 147 K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_TXD1.RGMII_TXD1 / 148 K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_TXD2.RGMII_TXD2 / 149 K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_TXD3.RGMII_TXD3 */ [all …]
D	omap3-n950.dts	46 OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN \| MUX_MODE1) /* mcspi4_clk / 47 OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT \| MUX_MODE1) / mcspi4_simo / 48 OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN \| MUX_MODE1) / mcspi4_somi / 49 OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT \| MUX_MODE1) / mcspi4_cs0 / 57 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT \| MUX_MODE1) / dsi_dx0 - data0+ / 58 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT \| MUX_MODE1) / dsi_dy0 - data0- / 59 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT \| MUX_MODE1) / dsi_dx1 - clk+ / 60 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT \| MUX_MODE1) / dsi_dy1 - clk- / 61 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT \| MUX_MODE1) / dsi_dx2 - data1+ / 62 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT \| MUX_MODE1) / dsi_dy2 - data1- */
D	am335x-nano.dts	78 AM33XX_IOPAD(0x8a4, PIN_OUTPUT \| MUX_MODE1) /* lcd_data1.gpmc_a1 / 79 AM33XX_IOPAD(0x8a8, PIN_OUTPUT \| MUX_MODE1) / lcd_data2.gpmc_a2 / 80 AM33XX_IOPAD(0x8ac, PIN_OUTPUT \| MUX_MODE1) / lcd_data3.gpmc_a3 / 81 AM33XX_IOPAD(0x8b0, PIN_OUTPUT \| MUX_MODE1) / lcd_data4.gpmc_a4 / 82 AM33XX_IOPAD(0x8b4, PIN_OUTPUT \| MUX_MODE1) / lcd_data5.gpmc_a5 / 83 AM33XX_IOPAD(0x8b8, PIN_OUTPUT \| MUX_MODE1) / lcd_data6.gpmc_a6 / 84 AM33XX_IOPAD(0x8bc, PIN_OUTPUT \| MUX_MODE1) / lcd_data7.gpmc_a7 / 86 AM33XX_IOPAD(0x8e0, PIN_OUTPUT \| MUX_MODE1) / lcd_vsync.gpmc_a8 / 87 AM33XX_IOPAD(0x8e4, PIN_OUTPUT \| MUX_MODE1) / lcd_hsync.gpmc_a9 / 88 AM33XX_IOPAD(0x8e8, PIN_OUTPUT \| MUX_MODE1) / lcd_pclk.gpmc_a10 */ [all …]
D	am335x-chiliboard.dts	48 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN \| MUX_MODE1) /* mii1_crs.rmii1_crs / 49 AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP \| MUX_MODE1) / mii1_rxerr.rmii1_rxerr / 50 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN \| MUX_MODE1) / mii1_txen.rmii1_txen / 51 AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN \| MUX_MODE1) / mii1_txd1.rmii1_txd1 / 52 AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN \| MUX_MODE1) / mii1_txd0.rmii1_txd0 / 53 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP \| MUX_MODE1) / mii1_rxd1.rmii1_rxd1 / 54 AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP \| MUX_MODE1) / mii1_rxd0.rmii1_rxd0 */
D	omap2420-n810.dts	`28 OMAP2420_CORE_IOPAD(0x0124, PIN_INPUT \| MUX_MODE1) /* eac_ac_sclk.mcbsp2_clkx / 29 OMAP2420_CORE_IOPAD(0x0125, PIN_INPUT \| MUX_MODE1) / eac_ac_fs.mcbsp2_fsx / 30 OMAP2420_CORE_IOPAD(0x0126, PIN_INPUT \| MUX_MODE1) / eac_ac_din.mcbsp2_dr / 31 OMAP2420_CORE_IOPAD(0x0127, PIN_OUTPUT \| MUX_MODE1) / eac_ac_dout.mcbsp2_dx */`
D	omap3-cm-t3530.dts	`34 OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT \| MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 / 35 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT \| MUX_MODE1) / sdmmc2_dat5.sdmmc2_dir_dat1 / 36 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT \| MUX_MODE1) / sdmmc2_dat6.sdmmc2_dir_cmd / 37 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT \| MUX_MODE1) / sdmmc2_dat7.sdmmc2_clkin */`
D	am335x-sbc-t335.dts	`73 AM33XX_IOPAD(0x820, PIN_OUTPUT \| MUX_MODE1) 75 AM33XX_IOPAD(0x824, PIN_OUTPUT \| MUX_MODE1) 77 AM33XX_IOPAD(0x828, PIN_OUTPUT \| MUX_MODE1) 79 AM33XX_IOPAD(0x82c, PIN_OUTPUT \| MUX_MODE1) 81 AM33XX_IOPAD(0x830, PIN_OUTPUT \| MUX_MODE1) 83 AM33XX_IOPAD(0x834, PIN_OUTPUT \| MUX_MODE1) 85 AM33XX_IOPAD(0x838, PIN_OUTPUT \| MUX_MODE1) 87 AM33XX_IOPAD(0x83c, PIN_OUTPUT \| MUX_MODE1)`
D	am57xx-cl-som-am57x.dts	118 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a23.mmc2_clk / 119 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_cs1.mmc2_cmd / 120 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a24.mmc2_dat0 / 121 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a25.mmc2_dat1 / 122 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a26.mmc2_dat2 / 123 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a27.mmc2_dat3 / 124 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a19.mmc2_dat4 / 125 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a20.mmc2_dat5 / 126 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a21.mmc2_dat6 / 127 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_a22.mmc2_dat7 */ [all …]
D	am335x-pepper.dts	247 AM33XX_IOPAD(0x820, PIN_OUTPUT \| MUX_MODE1) /* gpmc_ad8.lcd_data16 / 248 AM33XX_IOPAD(0x824, PIN_OUTPUT \| MUX_MODE1) / gpmc_ad9.lcd_data17 / 249 AM33XX_IOPAD(0x828, PIN_OUTPUT \| MUX_MODE1) / gpmc_ad10.lcd_data18 / 250 AM33XX_IOPAD(0x82c, PIN_OUTPUT \| MUX_MODE1) / gpmc_ad11.lcd_data19 / 251 AM33XX_IOPAD(0x830, PIN_OUTPUT \| MUX_MODE1) / gpmc_ad12.lcd_data20 / 252 AM33XX_IOPAD(0x834, PIN_OUTPUT \| MUX_MODE1) / gpmc_ad13.lcd_data21 / 253 AM33XX_IOPAD(0x838, PIN_OUTPUT \| MUX_MODE1) / gpmc_ad14.lcd_data22 / 254 AM33XX_IOPAD(0x83c, PIN_OUTPUT \| MUX_MODE1) / gpmc_ad15.lcd_data23 / 372 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_ad0.mmc1_dat0 / 373 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_ad1.mmc1_dat1 */ [all …]
D	keystone-k2g-ice.dts	288 K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) /* MII_RXD1.RGMII_RXD1 / 289 K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_RXD2.RGMII_RXD2 / 290 K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_RXD3.RGMII_RXD3 / 291 K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_RXD0.RGMII_RXD0 / 292 K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_TXD0.RGMII_TXD0 / 293 K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_TXD1.RGMII_TXD1 / 294 K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_TXD2.RGMII_TXD2 / 295 K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_TXD3.RGMII_TXD3 / 296 K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_TXCLK.RGMII_TXC / 297 K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D \| PULL_DISABLE \| MUX_MODE1) / MII_TXEN.RGMII_TXCTL */ [all …]
D	am335x-boneblue.dts	181 AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP \| MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd / 182 AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLDOWN \| MUX_MODE1) / (B17) spi0_d0.uart2_txd / 211 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP \| MUX_MODE1) / (U7) gpmc_ad0.mmc1_dat0 / 212 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP \| MUX_MODE1) / (V7) gpmc_ad1.mmc1_dat1 / 213 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP \| MUX_MODE1) / (R8) gpmc_ad2.mmc1_dat2 / 214 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP \| MUX_MODE1) / (T8) gpmc_ad3.mmc1_dat3 / 215 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP \| MUX_MODE1) / (U8) gpmc_ad4.mmc1_dat4 / 216 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP \| MUX_MODE1) / (V8) gpmc_ad5.mmc1_dat5 / 217 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP \| MUX_MODE1) / (R9) gpmc_ad6.mmc1_dat6 / 218 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP \| MUX_MODE1) / (T9) gpmc_ad7.mmc1_dat7 */ [all …]
D	omap3-igep0030-common.dtsi	`61 OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT \| MUX_MODE1) /* mcbsp3_dx.uart2_cts / 62 OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT \| MUX_MODE1) / mcbsp3_dr.uart2_rts / 63 OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT \| MUX_MODE1) / mcbsp3_clk.uart2_tx / 64 OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT \| MUX_MODE1) / mcbsp3_fsx.uart2_rx */`
D	am335x-phycore-som.dtsi	60 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN \| MUX_MODE1) /* mii1_crs.rmii1_crs_dv / 61 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN \| MUX_MODE1) / mii1_rxerr.rmii1_rxerr / 62 AM33XX_IOPAD(0x914, PIN_OUTPUT \| MUX_MODE1) / mii1_txen.rmii1_txen / 63 AM33XX_IOPAD(0x924, PIN_OUTPUT \| MUX_MODE1) / mii1_txd1.rmii1_txd1 / 64 AM33XX_IOPAD(0x928, PIN_OUTPUT \| MUX_MODE1) / mii1_txd0.rmii1_txd0 / 65 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN \| MUX_MODE1) / mii1_rxd1.rmii1_rxd1 / 66 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN \| MUX_MODE1) / mii1_rxd0.rmii1_rxd0 */
D	am335x-icev2.dts	200 AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP \| MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd / 201 AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP \| MUX_MODE1) / (L16) gmii1_rxd2.uart3_txd / 208 AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP \| MUX_MODE1)) / mii1_crs.rmii1_crs_dv / 210 AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP \| MUX_MODE1)) / mii1_rxd0.rmii1_rxd0 / 211 AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP \| MUX_MODE1)) / mii1_rxd1.rmii1_rxd1 / 212 AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP \| MUX_MODE1)) / mii1_rxerr.rmii1_rxerr / 213 AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN \| MUX_MODE1)) / mii1_txd0.rmii1_txd0 / 214 AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN \| MUX_MODE1)) / mii1_txd1.rmii1_txd1 / 215 AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN \| MUX_MODE1)) / mii1_txen.rmii1_txen / 218 AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP \| MUX_MODE1)) / mii1_col.rmii2_refclk */
D	am335x-shc.dts	457 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP \| MUX_MODE1) 458 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP \| MUX_MODE1) 459 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP \| MUX_MODE1) 460 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP \| MUX_MODE1) 461 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP \| MUX_MODE1) 462 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP \| MUX_MODE1) 463 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP \| MUX_MODE1) 464 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP \| MUX_MODE1) 512 AM33XX_IOPAD(0x950, PIN_INPUT \| MUX_MODE1) 513 AM33XX_IOPAD(0x954, PIN_OUTPUT \| MUX_MODE1)
D	am335x-bone-common.dtsi	178 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_ad0.mmc1_dat0 / 179 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_ad1.mmc1_dat1 / 180 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_ad2.mmc1_dat2 / 181 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_ad3.mmc1_dat3 / 182 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_ad4.mmc1_dat4 / 183 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_ad5.mmc1_dat5 / 184 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_ad6.mmc1_dat6 / 185 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP \| MUX_MODE1) / gpmc_ad7.mmc1_dat7 */
D	am43x-epos-evm.dts	193 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN \| MUX_MODE1) /* mii1_crs.rmii1_crs / 194 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN \| MUX_MODE1) / mii1_rxerr.rmii1_rxerr / 195 AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN \| MUX_MODE1) / mii1_txen.rmii1_txen / 196 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN \| MUX_MODE1) / mii1_rxdv.rmii1_rxdv / 197 AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN \| MUX_MODE1) / mii1_txd1.rmii1_txd1 / 198 AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN \| MUX_MODE1) / mii1_txd0.rmii1_txd0 / 199 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN \| MUX_MODE1) / mii1_rxd1.rmii1_rxd1 / 200 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN \| MUX_MODE1) / mii1_rxd0.rmii1_rxd0 / 414 AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP \| MUX_MODE1) / cam1_wen.hdq_gpio / 420 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP \| MUX_MODE1) /gpmc ad 8 -> DSS DATA 23 */ [all …]

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