Searched refs:MSR_TM (Results 1 – 12 of 12) sorted by relevance
57 (newmsr & MSR_TM))); in kvmhv_p9_tm_emulation()104 (newmsr & MSR_TM))); in kvmhv_p9_tm_emulation()124 if (!(msr & MSR_TM)) { in kvmhv_p9_tm_emulation()153 if (!(msr & MSR_TM)) { in kvmhv_p9_tm_emulation()190 if (!(msr & MSR_TM)) { in kvmhv_p9_tm_emulation()
34 if (!(MSR_TM_TRANSACTIONAL(newmsr) && (newmsr & MSR_TM))) in kvmhv_p9_tm_emulation_early()71 if (!(MSR_TM_TRANSACTIONAL(newmsr) && (newmsr & MSR_TM))) in kvmhv_p9_tm_emulation_early()86 if (!(vcpu->arch.hfscr & HFSCR_TM) || !(msr & MSR_TM)) in kvmhv_p9_tm_emulation_early()
290 if (((cur_msr & MSR_TM) == 0) && in kvmppc_core_emulate_op_pr()291 ((srr1 & MSR_TM) == 0) && in kvmppc_core_emulate_op_pr()489 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { in kvmppc_core_emulate_op_pr()527 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { in kvmppc_core_emulate_op_pr()553 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { in kvmppc_core_emulate_op_pr()587 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { in kvmppc_core_emulate_op_pr()783 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { in kvmppc_core_emulate_mtspr_pr()961 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { in kvmppc_core_emulate_mfspr_pr()
199 MSR_TM | MSR_TS_MASK; in kvmppc_recalc_shadow_msr()218 smsr &= ~MSR_TM; in kvmppc_recalc_shadow_msr()362 if (kvmppc_get_msr(vcpu) & MSR_TM) { in kvmppc_restore_tm_pr()374 if (kvmppc_get_msr(vcpu) & MSR_TM) { in kvmppc_restore_tm_pr()534 if (kvmppc_get_msr(vcpu) & MSR_TM) in kvmppc_set_msr_pr()985 guest_fac_enabled = kvmppc_get_msr(vcpu) & MSR_TM; in kvmppc_handle_fac()
227 li r6, MSR_TM >> 32
3430 (current->thread.regs->msr & MSR_TM)) { in kvmppc_vcpu_run_hv()3437 mtmsr(mfmsr() | MSR_TM); in kvmppc_vcpu_run_hv()3441 current->thread.regs->msr &= ~MSR_TM; in kvmppc_vcpu_run_hv()
53 li r3, MSR_TM >> 3264 li r3, MSR_TM >> 32
867 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); in tm_enabled()968 if (!(thread->regs->msr & MSR_TM)) in tm_recheckpoint()1037 prev->thread.regs->msr &= ~MSR_TM; in __switch_to_tm()1394 {MSR_TM, "E"},1407 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { in print_tm_bits()
482 regs->msr |= MSR_TM; in restore_tm_sigcontexts()
1608 regs->msr |= MSR_TM; in tm_unavailable()
116 #define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */ macro
1837 if (msr & MSR_TM) { in dump_207_sprs()
