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Searched refs:MPLL_FUNC_CNTL_1 (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/
Diceland_smumgr.c1077 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf); in iceland_calculate_mclk_params()
1079 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac); in iceland_calculate_mclk_params()
1081 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode); in iceland_calculate_mclk_params()
Dtonga_smumgr.c813 MPLL_FUNC_CNTL_1, CLKF, in tonga_calculate_mclk_params()
816 MPLL_FUNC_CNTL_1, CLKFRAC, in tonga_calculate_mclk_params()
819 MPLL_FUNC_CNTL_1, VCO_MODE, in tonga_calculate_mclk_params()
Dci_smumgr.c1050 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf); in ci_calculate_mclk_params()
1052 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac); in ci_calculate_mclk_params()
1054 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode); in ci_calculate_mclk_params()
/Linux-v4.19/drivers/gpu/drm/radeon/
Dsid.h615 #define MPLL_FUNC_CNTL_1 0x2bb8 macro
Dcikd.h738 #define MPLL_FUNC_CNTL_1 0x2bb8 macro
Dsi_dpm.c3580 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in si_read_clock_registers()
Dci_dpm.c1889 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in ci_read_clock_registers()
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dsid.h617 #define MPLL_FUNC_CNTL_1 0xAEE macro
Dsi_dpm.c4041 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in si_read_clock_registers()