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Searched refs:MLX5_ST_SZ_DW (Results 1 – 25 of 44) sorted by relevance

12

/Linux-v4.19/drivers/net/ethernet/mellanox/mlx5/core/
Dport.c80 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0}; in mlx5_query_pcam_reg()
92 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0}; in mlx5_query_mcam_reg()
104 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {}; in mlx5_query_qcam_reg()
140 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0}; in mlx5_query_port_ptys()
151 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0}; in mlx5_set_port_beacon()
152 u32 out[MLX5_ST_SZ_DW(mlcr_reg)]; in mlx5_set_port_beacon()
163 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_proto_cap()
182 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_proto_admin()
201 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_link_width_oper()
217 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_eth_proto_oper()
[all …]
Dtransobj.c39 u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; in mlx5_core_alloc_transport_domain()
40 u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; in mlx5_core_alloc_transport_domain()
57 u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {0}; in mlx5_core_dealloc_transport_domain()
58 u32 out[MLX5_ST_SZ_DW(dealloc_transport_domain_out)] = {0}; in mlx5_core_dealloc_transport_domain()
69 u32 out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; in mlx5_core_create_rq()
83 u32 out[MLX5_ST_SZ_DW(modify_rq_out)]; in mlx5_core_modify_rq()
95 u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {0}; in mlx5_core_destroy_rq()
96 u32 out[MLX5_ST_SZ_DW(destroy_rq_out)] = {0}; in mlx5_core_destroy_rq()
106 u32 in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; in mlx5_core_query_rq()
118 u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; in mlx5_core_create_sq()
[all …]
Dqp.c198 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0}; in mlx5_core_create_dct()
199 u32 din[MLX5_ST_SZ_DW(destroy_dct_in)] = {0}; in mlx5_core_create_dct()
200 u32 dout[MLX5_ST_SZ_DW(destroy_dct_out)] = {0}; in mlx5_core_create_dct()
232 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; in mlx5_core_create_qp()
233 u32 dout[MLX5_ST_SZ_DW(destroy_qp_out)]; in mlx5_core_create_qp()
234 u32 din[MLX5_ST_SZ_DW(destroy_qp_in)]; in mlx5_core_create_qp()
272 u32 out[MLX5_ST_SZ_DW(drain_dct_out)] = {0}; in mlx5_core_drain_dct()
273 u32 in[MLX5_ST_SZ_DW(drain_dct_in)] = {0}; in mlx5_core_drain_dct()
285 u32 out[MLX5_ST_SZ_DW(destroy_dct_out)] = {0}; in mlx5_core_destroy_dct()
286 u32 in[MLX5_ST_SZ_DW(destroy_dct_in)] = {0}; in mlx5_core_destroy_dct()
[all …]
Dfs_cmd.c118 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {0}; in mlx5_cmd_update_root_ft()
119 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {0}; in mlx5_cmd_update_root_ft()
156 u32 out[MLX5_ST_SZ_DW(create_flow_table_out)] = {0}; in mlx5_cmd_create_flow_table()
157 u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {0}; in mlx5_cmd_create_flow_table()
205 u32 in[MLX5_ST_SZ_DW(destroy_flow_table_in)] = {0}; in mlx5_cmd_destroy_flow_table()
206 u32 out[MLX5_ST_SZ_DW(destroy_flow_table_out)] = {0}; in mlx5_cmd_destroy_flow_table()
224 u32 in[MLX5_ST_SZ_DW(modify_flow_table_in)] = {0}; in mlx5_cmd_modify_flow_table()
225 u32 out[MLX5_ST_SZ_DW(modify_flow_table_out)] = {0}; in mlx5_cmd_modify_flow_table()
270 u32 out[MLX5_ST_SZ_DW(create_flow_group_out)] = {0}; in mlx5_cmd_create_flow_group()
294 u32 out[MLX5_ST_SZ_DW(destroy_flow_group_out)] = {0}; in mlx5_cmd_destroy_flow_group()
[all …]
Dpd.c41 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; in mlx5_core_alloc_pd()
42 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; in mlx5_core_alloc_pd()
55 u32 out[MLX5_ST_SZ_DW(dealloc_pd_out)] = {0}; in mlx5_core_dealloc_pd()
56 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {0}; in mlx5_core_dealloc_pd()
Dfw.c43 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {0}; in mlx5_cmd_query_adapter()
210 u32 out[MLX5_ST_SZ_DW(init_hca_out)] = {0}; in mlx5_cmd_init_hca()
211 u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {0}; in mlx5_cmd_init_hca()
227 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; in mlx5_cmd_teardown_hca()
228 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; in mlx5_cmd_teardown_hca()
236 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; in mlx5_cmd_force_teardown_hca()
237 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; in mlx5_cmd_force_teardown_hca()
276 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_set()
277 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_set()
294 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_query()
[all …]
Dmr.c59 u32 lout[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; in mlx5_core_create_mkey_cb()
117 u32 out[MLX5_ST_SZ_DW(destroy_mkey_out)] = {0}; in mlx5_core_destroy_mkey()
118 u32 in[MLX5_ST_SZ_DW(destroy_mkey_in)] = {0}; in mlx5_core_destroy_mkey()
140 u32 in[MLX5_ST_SZ_DW(query_mkey_in)] = {0}; in mlx5_core_query_mkey()
162 u32 out[MLX5_ST_SZ_DW(create_psv_out)] = {0}; in mlx5_core_create_psv()
163 u32 in[MLX5_ST_SZ_DW(create_psv_in)] = {0}; in mlx5_core_create_psv()
186 u32 out[MLX5_ST_SZ_DW(destroy_psv_out)] = {0}; in mlx5_core_destroy_psv()
187 u32 in[MLX5_ST_SZ_DW(destroy_psv_in)] = {0}; in mlx5_core_destroy_psv()
Dmcg.c42 u32 out[MLX5_ST_SZ_DW(attach_to_mcg_out)] = {0}; in mlx5_core_attach_mcg()
43 u32 in[MLX5_ST_SZ_DW(attach_to_mcg_in)] = {0}; in mlx5_core_attach_mcg()
56 u32 out[MLX5_ST_SZ_DW(detach_from_mcg_out)] = {0}; in mlx5_core_detach_mcg()
57 u32 in[MLX5_ST_SZ_DW(detach_from_mcg_in)] = {0}; in mlx5_core_detach_mcg()
Dcq.c92 u32 dout[MLX5_ST_SZ_DW(destroy_cq_out)]; in mlx5_core_create_cq()
93 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; in mlx5_core_create_cq()
94 u32 din[MLX5_ST_SZ_DW(destroy_cq_in)]; in mlx5_core_create_cq()
154 u32 out[MLX5_ST_SZ_DW(destroy_cq_out)] = {0}; in mlx5_core_destroy_cq()
155 u32 in[MLX5_ST_SZ_DW(destroy_cq_in)] = {0}; in mlx5_core_destroy_cq()
185 u32 in[MLX5_ST_SZ_DW(query_cq_in)] = {0}; in mlx5_core_query_cq()
196 u32 out[MLX5_ST_SZ_DW(modify_cq_out)] = {0}; in mlx5_core_modify_cq()
208 u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {0}; in mlx5_core_modify_cq_moderation()
Drl.c43 u32 in[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {0}; in mlx5_create_scheduling_element_cmd()
44 u32 out[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {0}; in mlx5_create_scheduling_element_cmd()
69 u32 in[MLX5_ST_SZ_DW(modify_scheduling_element_in)] = {0}; in mlx5_modify_scheduling_element_cmd()
70 u32 out[MLX5_ST_SZ_DW(modify_scheduling_element_in)] = {0}; in mlx5_modify_scheduling_element_cmd()
91 u32 in[MLX5_ST_SZ_DW(destroy_scheduling_element_in)] = {0}; in mlx5_destroy_scheduling_element_cmd()
92 u32 out[MLX5_ST_SZ_DW(destroy_scheduling_element_in)] = {0}; in mlx5_destroy_scheduling_element_cmd()
132 u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {0}; in mlx5_set_pp_rate_limit_cmd()
133 u32 out[MLX5_ST_SZ_DW(set_pp_rate_limit_out)] = {0}; in mlx5_set_pp_rate_limit_cmd()
Dsrq.c155 u32 create_out[MLX5_ST_SZ_DW(create_srq_out)] = {0}; in create_srq_cmd()
190 u32 srq_in[MLX5_ST_SZ_DW(destroy_srq_in)] = {0}; in destroy_srq_cmd()
191 u32 srq_out[MLX5_ST_SZ_DW(destroy_srq_out)] = {0}; in destroy_srq_cmd()
204 u32 srq_in[MLX5_ST_SZ_DW(arm_rq_in)] = {0}; in arm_srq_cmd()
205 u32 srq_out[MLX5_ST_SZ_DW(arm_rq_out)] = {0}; in arm_srq_cmd()
219 u32 srq_in[MLX5_ST_SZ_DW(query_srq_in)] = {0}; in query_srq_cmd()
249 u32 create_out[MLX5_ST_SZ_DW(create_xrc_srq_out)]; in create_xrc_srq_cmd()
288 u32 xrcsrq_in[MLX5_ST_SZ_DW(destroy_xrc_srq_in)] = {0}; in destroy_xrc_srq_cmd()
289 u32 xrcsrq_out[MLX5_ST_SZ_DW(destroy_xrc_srq_out)] = {0}; in destroy_xrc_srq_cmd()
302 u32 xrcsrq_in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {0}; in arm_xrc_srq_cmd()
[all …]
Dlag.c80 u32 in[MLX5_ST_SZ_DW(create_lag_in)] = {0}; in mlx5_cmd_create_lag()
81 u32 out[MLX5_ST_SZ_DW(create_lag_out)] = {0}; in mlx5_cmd_create_lag()
95 u32 in[MLX5_ST_SZ_DW(modify_lag_in)] = {0}; in mlx5_cmd_modify_lag()
96 u32 out[MLX5_ST_SZ_DW(modify_lag_out)] = {0}; in mlx5_cmd_modify_lag()
110 u32 in[MLX5_ST_SZ_DW(destroy_lag_in)] = {0}; in mlx5_cmd_destroy_lag()
111 u32 out[MLX5_ST_SZ_DW(destroy_lag_out)] = {0}; in mlx5_cmd_destroy_lag()
120 u32 in[MLX5_ST_SZ_DW(create_vport_lag_in)] = {0}; in mlx5_cmd_create_vport_lag()
121 u32 out[MLX5_ST_SZ_DW(create_vport_lag_out)] = {0}; in mlx5_cmd_create_vport_lag()
131 u32 in[MLX5_ST_SZ_DW(destroy_vport_lag_in)] = {0}; in mlx5_cmd_destroy_vport_lag()
132 u32 out[MLX5_ST_SZ_DW(destroy_vport_lag_out)] = {0}; in mlx5_cmd_destroy_vport_lag()
[all …]
Dvport.c45 u32 in[MLX5_ST_SZ_DW(query_vport_state_in)] = {0}; in _mlx5_query_vport_state()
59 u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {0}; in mlx5_query_vport_state()
69 u32 in[MLX5_ST_SZ_DW(modify_vport_state_in)] = {0}; in mlx5_modify_vport_admin_state()
70 u32 out[MLX5_ST_SZ_DW(modify_vport_state_out)] = {0}; in mlx5_modify_vport_admin_state()
86 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; in mlx5_query_nic_vport_context()
100 u32 out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {0}; in mlx5_modify_nic_vport_context()
110 u32 out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; in mlx5_query_nic_vport_min_inline()
141 u32 in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)] = {0}; in mlx5_modify_nic_vport_min_inline()
263 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; in mlx5_query_nic_vport_mac_list()
326 u32 out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)]; in mlx5_modify_nic_vport_mac_list()
[all …]
Dpagealloc.c137 u32 out[MLX5_ST_SZ_DW(query_pages_out)] = {0}; in mlx5_cmd_query_pages()
138 u32 in[MLX5_ST_SZ_DW(query_pages_in)] = {0}; in mlx5_cmd_query_pages()
257 u32 out[MLX5_ST_SZ_DW(manage_pages_out)] = {0}; in page_notify_fail()
258 u32 in[MLX5_ST_SZ_DW(manage_pages_in)] = {0}; in page_notify_fail()
274 u32 out[MLX5_ST_SZ_DW(manage_pages_out)] = {0}; in give_pages()
369 u32 in[MLX5_ST_SZ_DW(manage_pages_in)] = {0}; in reclaim_pages()
Duar.c42 u32 out[MLX5_ST_SZ_DW(alloc_uar_out)] = {0}; in mlx5_cmd_alloc_uar()
43 u32 in[MLX5_ST_SZ_DW(alloc_uar_in)] = {0}; in mlx5_cmd_alloc_uar()
56 u32 out[MLX5_ST_SZ_DW(dealloc_uar_out)] = {0}; in mlx5_cmd_free_uar()
57 u32 in[MLX5_ST_SZ_DW(dealloc_uar_in)] = {0}; in mlx5_cmd_free_uar()
Den_stats.c269 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)]; in mlx5e_grp_q_update_stats()
329 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {0}; in mlx5e_grp_vnic_env_update_stats()
418 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0}; in mlx5e_grp_vport_update_stats()
483 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; in mlx5e_grp_802_3_update_stats()
534 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; in mlx5e_grp_2863_update_stats()
595 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; in mlx5e_grp_2819_update_stats()
660 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; in mlx5e_grp_phy_update_stats()
723 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; in mlx5e_grp_eth_ext_update_stats()
827 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0}; in mlx5e_grp_pcie_update_stats()
1033 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; in mlx5e_grp_per_prio_update_stats()
/Linux-v4.19/drivers/net/ethernet/mellanox/mlx5/core/fpga/
Dcmd.c41 #define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
76 u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0}; in mlx5_fpga_caps()
85 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_ctrl_op()
86 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_ctrl_op()
128 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_query()
129 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_query()
146 u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {0}; in mlx5_fpga_create_qp()
147 u32 out[MLX5_ST_SZ_DW(fpga_create_qp_out)]; in mlx5_fpga_create_qp()
168 u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {0}; in mlx5_fpga_modify_qp()
169 u32 out[MLX5_ST_SZ_DW(fpga_modify_qp_out)]; in mlx5_fpga_modify_qp()
[all …]
/Linux-v4.19/drivers/infiniband/hw/mlx5/
Dcmd.c37 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {0}; in mlx5_cmd_dump_fill_mkey()
38 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {0}; in mlx5_cmd_dump_fill_mkey()
52 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {}; in mlx5_cmd_null_mkey()
53 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {}; in mlx5_cmd_null_mkey()
68 u32 in[MLX5_ST_SZ_DW(query_cong_params_in)] = { }; in mlx5_cmd_query_cong_params()
80 u32 out[MLX5_ST_SZ_DW(modify_cong_params_out)] = { }; in mlx5_cmd_modify_cong_params()
94 u32 out[MLX5_ST_SZ_DW(alloc_memic_out)] = {}; in mlx5_cmd_alloc_memic()
95 u32 in[MLX5_ST_SZ_DW(alloc_memic_in)] = {}; in mlx5_cmd_alloc_memic()
165 u32 out[MLX5_ST_SZ_DW(dealloc_memic_out)] = {0}; in mlx5_cmd_dealloc_memic()
166 u32 in[MLX5_ST_SZ_DW(dealloc_memic_in)] = {0}; in mlx5_cmd_dealloc_memic()
[all …]
Ddevx.c19 #define MLX5_MAX_DESTROY_INBOX_SIZE_DW MLX5_ST_SZ_DW(delete_fte_in)
34 u32 dinbox[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)];
40 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
50 u32 in[MLX5_ST_SZ_DW(create_uctx_in)] = {0}; in mlx5_ib_devx_create()
51 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; in mlx5_ib_devx_create()
80 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; in mlx5_ib_devx_destroy()
81 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; in mlx5_ib_devx_destroy()
703 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in devx_obj_cleanup()
726 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in UVERBS_HANDLER()
975 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in devx_umem_cleanup()
/Linux-v4.19/drivers/net/ethernet/mellanox/mlx5/core/diag/
Dfs_tracepoint.h74 __array(u32, mask_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
75 __array(u32, mask_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
76 __array(u32, mask_misc, MLX5_ST_SZ_DW(fte_match_set_misc))
157 __array(u32, mask_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
158 __array(u32, mask_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
159 __array(u32, mask_misc, MLX5_ST_SZ_DW(fte_match_set_misc))
160 __array(u32, value_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
161 __array(u32, value_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
162 __array(u32, value_misc, MLX5_ST_SZ_DW(fte_match_set_misc))
Dfw_tracer.c41 u32 out[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_query_mtrc_caps()
42 u32 in[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_query_mtrc_caps()
84 u32 in[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_set_mtrc_caps_trace_owner()
95 u32 out[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_fw_tracer_ownership_acquire()
116 u32 out[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_fw_tracer_ownership_release()
251 u32 in[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_tracer_read_strings_db()
324 u32 out[MLX5_ST_SZ_DW(mtrc_ctrl)] = {0}; in mlx5_fw_tracer_arm()
325 u32 in[MLX5_ST_SZ_DW(mtrc_ctrl)] = {0}; in mlx5_fw_tracer_arm()
703 u32 out[MLX5_ST_SZ_DW(mtrc_conf)] = {0}; in mlx5_fw_tracer_set_mtrc_conf()
704 u32 in[MLX5_ST_SZ_DW(mtrc_conf)] = {0}; in mlx5_fw_tracer_set_mtrc_conf()
[all …]
/Linux-v4.19/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dmpfs.c43 u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {0}; in set_l2table_entry_cmd()
44 u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)] = {0}; in set_l2table_entry_cmd()
58 u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)] = {0}; in del_l2table_entry_cmd()
59 u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)] = {0}; in del_l2table_entry_cmd()
Dvxlan.c61 u32 in[MLX5_ST_SZ_DW(add_vxlan_udp_dport_in)] = {0}; in mlx5_vxlan_core_add_port_cmd()
62 u32 out[MLX5_ST_SZ_DW(add_vxlan_udp_dport_out)] = {0}; in mlx5_vxlan_core_add_port_cmd()
72 u32 in[MLX5_ST_SZ_DW(delete_vxlan_udp_dport_in)] = {0}; in mlx5_vxlan_core_del_port_cmd()
73 u32 out[MLX5_ST_SZ_DW(delete_vxlan_udp_dport_out)] = {0}; in mlx5_vxlan_core_del_port_cmd()
Dgid.c127 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; in mlx5_core_roce_gid_set()
128 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; in mlx5_core_roce_gid_set()
/Linux-v4.19/include/linux/mlx5/
Dfs.h84 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
85 u32 match_value[MLX5_ST_SZ_DW(fte_match_param)];

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