1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/radix-tree.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49
50 #include <linux/mlx5/device.h>
51 #include <linux/mlx5/doorbell.h>
52 #include <linux/mlx5/srq.h>
53 #include <linux/timecounter.h>
54 #include <linux/ptp_clock_kernel.h>
55
56 enum {
57 MLX5_BOARD_ID_LEN = 64,
58 MLX5_MAX_NAME_LEN = 16,
59 };
60
61 enum {
62 /* one minute for the sake of bringup. Generally, commands must always
63 * complete and we may need to increase this timeout value
64 */
65 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
66 MLX5_CMD_WQ_MAX_NAME = 32,
67 };
68
69 enum {
70 CMD_OWNER_SW = 0x0,
71 CMD_OWNER_HW = 0x1,
72 CMD_STATUS_SUCCESS = 0,
73 };
74
75 enum mlx5_sqp_t {
76 MLX5_SQP_SMI = 0,
77 MLX5_SQP_GSI = 1,
78 MLX5_SQP_IEEE_1588 = 2,
79 MLX5_SQP_SNIFFER = 3,
80 MLX5_SQP_SYNC_UMR = 4,
81 };
82
83 enum {
84 MLX5_MAX_PORTS = 2,
85 };
86
87 enum {
88 MLX5_EQ_VEC_PAGES = 0,
89 MLX5_EQ_VEC_CMD = 1,
90 MLX5_EQ_VEC_ASYNC = 2,
91 MLX5_EQ_VEC_PFAULT = 3,
92 MLX5_EQ_VEC_COMP_BASE,
93 };
94
95 enum {
96 MLX5_MAX_IRQ_NAME = 32
97 };
98
99 enum {
100 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
101 MLX5_ATOMIC_MODE_CX = 2 << 16,
102 MLX5_ATOMIC_MODE_8B = 3 << 16,
103 MLX5_ATOMIC_MODE_16B = 4 << 16,
104 MLX5_ATOMIC_MODE_32B = 5 << 16,
105 MLX5_ATOMIC_MODE_64B = 6 << 16,
106 MLX5_ATOMIC_MODE_128B = 7 << 16,
107 MLX5_ATOMIC_MODE_256B = 8 << 16,
108 };
109
110 enum {
111 MLX5_REG_QPTS = 0x4002,
112 MLX5_REG_QETCR = 0x4005,
113 MLX5_REG_QTCT = 0x400a,
114 MLX5_REG_QPDPM = 0x4013,
115 MLX5_REG_QCAM = 0x4019,
116 MLX5_REG_DCBX_PARAM = 0x4020,
117 MLX5_REG_DCBX_APP = 0x4021,
118 MLX5_REG_FPGA_CAP = 0x4022,
119 MLX5_REG_FPGA_CTRL = 0x4023,
120 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
121 MLX5_REG_PCAP = 0x5001,
122 MLX5_REG_PMTU = 0x5003,
123 MLX5_REG_PTYS = 0x5004,
124 MLX5_REG_PAOS = 0x5006,
125 MLX5_REG_PFCC = 0x5007,
126 MLX5_REG_PPCNT = 0x5008,
127 MLX5_REG_PPTB = 0x500b,
128 MLX5_REG_PBMC = 0x500c,
129 MLX5_REG_PMAOS = 0x5012,
130 MLX5_REG_PUDE = 0x5009,
131 MLX5_REG_PMPE = 0x5010,
132 MLX5_REG_PELC = 0x500e,
133 MLX5_REG_PVLC = 0x500f,
134 MLX5_REG_PCMR = 0x5041,
135 MLX5_REG_PMLP = 0x5002,
136 MLX5_REG_PCAM = 0x507f,
137 MLX5_REG_NODE_DESC = 0x6001,
138 MLX5_REG_HOST_ENDIANNESS = 0x7004,
139 MLX5_REG_MCIA = 0x9014,
140 MLX5_REG_MLCR = 0x902b,
141 MLX5_REG_MTRC_CAP = 0x9040,
142 MLX5_REG_MTRC_CONF = 0x9041,
143 MLX5_REG_MTRC_STDB = 0x9042,
144 MLX5_REG_MTRC_CTRL = 0x9043,
145 MLX5_REG_MPCNT = 0x9051,
146 MLX5_REG_MTPPS = 0x9053,
147 MLX5_REG_MTPPSE = 0x9054,
148 MLX5_REG_MPEGC = 0x9056,
149 MLX5_REG_MCQI = 0x9061,
150 MLX5_REG_MCC = 0x9062,
151 MLX5_REG_MCDA = 0x9063,
152 MLX5_REG_MCAM = 0x907f,
153 };
154
155 enum mlx5_qpts_trust_state {
156 MLX5_QPTS_TRUST_PCP = 1,
157 MLX5_QPTS_TRUST_DSCP = 2,
158 };
159
160 enum mlx5_dcbx_oper_mode {
161 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
162 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
163 };
164
165 enum mlx5_dct_atomic_mode {
166 MLX5_ATOMIC_MODE_DCT_OFF = 20,
167 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF,
168 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF,
169 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF,
170 };
171
172 enum {
173 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
174 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
175 };
176
177 enum mlx5_page_fault_resume_flags {
178 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
179 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
180 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
181 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
182 };
183
184 enum dbg_rsc_type {
185 MLX5_DBG_RSC_QP,
186 MLX5_DBG_RSC_EQ,
187 MLX5_DBG_RSC_CQ,
188 };
189
190 enum port_state_policy {
191 MLX5_POLICY_DOWN = 0,
192 MLX5_POLICY_UP = 1,
193 MLX5_POLICY_FOLLOW = 2,
194 MLX5_POLICY_INVALID = 0xffffffff
195 };
196
197 struct mlx5_field_desc {
198 struct dentry *dent;
199 int i;
200 };
201
202 struct mlx5_rsc_debug {
203 struct mlx5_core_dev *dev;
204 void *object;
205 enum dbg_rsc_type type;
206 struct dentry *root;
207 struct mlx5_field_desc fields[0];
208 };
209
210 enum mlx5_dev_event {
211 MLX5_DEV_EVENT_SYS_ERROR,
212 MLX5_DEV_EVENT_PORT_UP,
213 MLX5_DEV_EVENT_PORT_DOWN,
214 MLX5_DEV_EVENT_PORT_INITIALIZED,
215 MLX5_DEV_EVENT_LID_CHANGE,
216 MLX5_DEV_EVENT_PKEY_CHANGE,
217 MLX5_DEV_EVENT_GUID_CHANGE,
218 MLX5_DEV_EVENT_CLIENT_REREG,
219 MLX5_DEV_EVENT_PPS,
220 MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT,
221 };
222
223 enum mlx5_port_status {
224 MLX5_PORT_UP = 1,
225 MLX5_PORT_DOWN = 2,
226 };
227
228 enum mlx5_eq_type {
229 MLX5_EQ_TYPE_COMP,
230 MLX5_EQ_TYPE_ASYNC,
231 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
232 MLX5_EQ_TYPE_PF,
233 #endif
234 };
235
236 struct mlx5_bfreg_info {
237 u32 *sys_pages;
238 int num_low_latency_bfregs;
239 unsigned int *count;
240
241 /*
242 * protect bfreg allocation data structs
243 */
244 struct mutex lock;
245 u32 ver;
246 bool lib_uar_4k;
247 u32 num_sys_pages;
248 u32 num_static_sys_pages;
249 u32 total_num_bfregs;
250 u32 num_dyn_bfregs;
251 };
252
253 struct mlx5_cmd_first {
254 __be32 data[4];
255 };
256
257 struct mlx5_cmd_msg {
258 struct list_head list;
259 struct cmd_msg_cache *parent;
260 u32 len;
261 struct mlx5_cmd_first first;
262 struct mlx5_cmd_mailbox *next;
263 };
264
265 struct mlx5_cmd_debug {
266 struct dentry *dbg_root;
267 struct dentry *dbg_in;
268 struct dentry *dbg_out;
269 struct dentry *dbg_outlen;
270 struct dentry *dbg_status;
271 struct dentry *dbg_run;
272 void *in_msg;
273 void *out_msg;
274 u8 status;
275 u16 inlen;
276 u16 outlen;
277 };
278
279 struct cmd_msg_cache {
280 /* protect block chain allocations
281 */
282 spinlock_t lock;
283 struct list_head head;
284 unsigned int max_inbox_size;
285 unsigned int num_ent;
286 };
287
288 enum {
289 MLX5_NUM_COMMAND_CACHES = 5,
290 };
291
292 struct mlx5_cmd_stats {
293 u64 sum;
294 u64 n;
295 struct dentry *root;
296 struct dentry *avg;
297 struct dentry *count;
298 /* protect command average calculations */
299 spinlock_t lock;
300 };
301
302 struct mlx5_cmd {
303 void *cmd_alloc_buf;
304 dma_addr_t alloc_dma;
305 int alloc_size;
306 void *cmd_buf;
307 dma_addr_t dma;
308 u16 cmdif_rev;
309 u8 log_sz;
310 u8 log_stride;
311 int max_reg_cmds;
312 int events;
313 u32 __iomem *vector;
314
315 /* protect command queue allocations
316 */
317 spinlock_t alloc_lock;
318
319 /* protect token allocations
320 */
321 spinlock_t token_lock;
322 u8 token;
323 unsigned long bitmask;
324 char wq_name[MLX5_CMD_WQ_MAX_NAME];
325 struct workqueue_struct *wq;
326 struct semaphore sem;
327 struct semaphore pages_sem;
328 int mode;
329 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
330 struct dma_pool *pool;
331 struct mlx5_cmd_debug dbg;
332 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
333 int checksum_disabled;
334 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
335 };
336
337 struct mlx5_port_caps {
338 int gid_table_len;
339 int pkey_table_len;
340 u8 ext_port_cap;
341 bool has_smi;
342 };
343
344 struct mlx5_cmd_mailbox {
345 void *buf;
346 dma_addr_t dma;
347 struct mlx5_cmd_mailbox *next;
348 };
349
350 struct mlx5_buf_list {
351 void *buf;
352 dma_addr_t map;
353 };
354
355 struct mlx5_frag_buf {
356 struct mlx5_buf_list *frags;
357 int npages;
358 int size;
359 u8 page_shift;
360 };
361
362 struct mlx5_frag_buf_ctrl {
363 struct mlx5_frag_buf frag_buf;
364 u32 sz_m1;
365 u16 frag_sz_m1;
366 u16 strides_offset;
367 u8 log_sz;
368 u8 log_stride;
369 u8 log_frag_strides;
370 };
371
372 struct mlx5_eq_tasklet {
373 struct list_head list;
374 struct list_head process_list;
375 struct tasklet_struct task;
376 /* lock on completion tasklet list */
377 spinlock_t lock;
378 };
379
380 struct mlx5_eq_pagefault {
381 struct work_struct work;
382 /* Pagefaults lock */
383 spinlock_t lock;
384 struct workqueue_struct *wq;
385 mempool_t *pool;
386 };
387
388 struct mlx5_cq_table {
389 /* protect radix tree */
390 spinlock_t lock;
391 struct radix_tree_root tree;
392 };
393
394 struct mlx5_eq {
395 struct mlx5_core_dev *dev;
396 struct mlx5_cq_table cq_table;
397 __be32 __iomem *doorbell;
398 u32 cons_index;
399 struct mlx5_frag_buf buf;
400 int size;
401 unsigned int irqn;
402 u8 eqn;
403 int nent;
404 u64 mask;
405 struct list_head list;
406 int index;
407 struct mlx5_rsc_debug *dbg;
408 enum mlx5_eq_type type;
409 union {
410 struct mlx5_eq_tasklet tasklet_ctx;
411 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
412 struct mlx5_eq_pagefault pf_ctx;
413 #endif
414 };
415 };
416
417 struct mlx5_core_psv {
418 u32 psv_idx;
419 struct psv_layout {
420 u32 pd;
421 u16 syndrome;
422 u16 reserved;
423 u16 bg;
424 u16 app_tag;
425 u32 ref_tag;
426 } psv;
427 };
428
429 struct mlx5_core_sig_ctx {
430 struct mlx5_core_psv psv_memory;
431 struct mlx5_core_psv psv_wire;
432 struct ib_sig_err err_item;
433 bool sig_status_checked;
434 bool sig_err_exists;
435 u32 sigerr_count;
436 };
437
438 enum {
439 MLX5_MKEY_MR = 1,
440 MLX5_MKEY_MW,
441 };
442
443 struct mlx5_core_mkey {
444 u64 iova;
445 u64 size;
446 u32 key;
447 u32 pd;
448 u32 type;
449 };
450
451 #define MLX5_24BIT_MASK ((1 << 24) - 1)
452
453 enum mlx5_res_type {
454 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
455 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
456 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
457 MLX5_RES_SRQ = 3,
458 MLX5_RES_XSRQ = 4,
459 MLX5_RES_XRQ = 5,
460 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
461 };
462
463 struct mlx5_core_rsc_common {
464 enum mlx5_res_type res;
465 atomic_t refcount;
466 struct completion free;
467 };
468
469 struct mlx5_core_srq {
470 struct mlx5_core_rsc_common common; /* must be first */
471 u32 srqn;
472 int max;
473 size_t max_gs;
474 size_t max_avail_gather;
475 int wqe_shift;
476 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
477
478 atomic_t refcount;
479 struct completion free;
480 };
481
482 struct mlx5_eq_table {
483 void __iomem *update_ci;
484 void __iomem *update_arm_ci;
485 struct list_head comp_eqs_list;
486 struct mlx5_eq pages_eq;
487 struct mlx5_eq async_eq;
488 struct mlx5_eq cmd_eq;
489 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
490 struct mlx5_eq pfault_eq;
491 #endif
492 int num_comp_vectors;
493 /* protect EQs list
494 */
495 spinlock_t lock;
496 };
497
498 struct mlx5_uars_page {
499 void __iomem *map;
500 bool wc;
501 u32 index;
502 struct list_head list;
503 unsigned int bfregs;
504 unsigned long *reg_bitmap; /* for non fast path bf regs */
505 unsigned long *fp_bitmap;
506 unsigned int reg_avail;
507 unsigned int fp_avail;
508 struct kref ref_count;
509 struct mlx5_core_dev *mdev;
510 };
511
512 struct mlx5_bfreg_head {
513 /* protect blue flame registers allocations */
514 struct mutex lock;
515 struct list_head list;
516 };
517
518 struct mlx5_bfreg_data {
519 struct mlx5_bfreg_head reg_head;
520 struct mlx5_bfreg_head wc_head;
521 };
522
523 struct mlx5_sq_bfreg {
524 void __iomem *map;
525 struct mlx5_uars_page *up;
526 bool wc;
527 u32 index;
528 unsigned int offset;
529 };
530
531 struct mlx5_core_health {
532 struct health_buffer __iomem *health;
533 __be32 __iomem *health_counter;
534 struct timer_list timer;
535 u32 prev;
536 int miss_counter;
537 bool sick;
538 /* wq spinlock to synchronize draining */
539 spinlock_t wq_lock;
540 struct workqueue_struct *wq;
541 unsigned long flags;
542 struct work_struct work;
543 struct delayed_work recover_work;
544 };
545
546 struct mlx5_qp_table {
547 /* protect radix tree
548 */
549 spinlock_t lock;
550 struct radix_tree_root tree;
551 };
552
553 struct mlx5_srq_table {
554 /* protect radix tree
555 */
556 spinlock_t lock;
557 struct radix_tree_root tree;
558 };
559
560 struct mlx5_mkey_table {
561 /* protect radix tree
562 */
563 rwlock_t lock;
564 struct radix_tree_root tree;
565 };
566
567 struct mlx5_vf_context {
568 int enabled;
569 u64 port_guid;
570 u64 node_guid;
571 enum port_state_policy policy;
572 };
573
574 struct mlx5_core_sriov {
575 struct mlx5_vf_context *vfs_ctx;
576 int num_vfs;
577 int enabled_vfs;
578 };
579
580 struct mlx5_irq_info {
581 cpumask_var_t mask;
582 char name[MLX5_MAX_IRQ_NAME];
583 };
584
585 struct mlx5_fc_stats {
586 struct rb_root counters;
587 struct list_head addlist;
588 /* protect addlist add/splice operations */
589 spinlock_t addlist_lock;
590
591 struct workqueue_struct *wq;
592 struct delayed_work work;
593 unsigned long next_query;
594 unsigned long sampling_interval; /* jiffies */
595 };
596
597 struct mlx5_mpfs;
598 struct mlx5_eswitch;
599 struct mlx5_lag;
600 struct mlx5_pagefault;
601
602 struct mlx5_rate_limit {
603 u32 rate;
604 u32 max_burst_sz;
605 u16 typical_pkt_sz;
606 };
607
608 struct mlx5_rl_entry {
609 struct mlx5_rate_limit rl;
610 u16 index;
611 u16 refcount;
612 };
613
614 struct mlx5_rl_table {
615 /* protect rate limit table */
616 struct mutex rl_lock;
617 u16 max_size;
618 u32 max_rate;
619 u32 min_rate;
620 struct mlx5_rl_entry *rl_entry;
621 };
622
623 enum port_module_event_status_type {
624 MLX5_MODULE_STATUS_PLUGGED = 0x1,
625 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
626 MLX5_MODULE_STATUS_ERROR = 0x3,
627 MLX5_MODULE_STATUS_NUM = 0x3,
628 };
629
630 enum port_module_event_error_type {
631 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
632 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
633 MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
634 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
635 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
636 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
637 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
638 MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
639 MLX5_MODULE_EVENT_ERROR_UNKNOWN,
640 MLX5_MODULE_EVENT_ERROR_NUM,
641 };
642
643 struct mlx5_port_module_event_stats {
644 u64 status_counters[MLX5_MODULE_STATUS_NUM];
645 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
646 };
647
648 struct mlx5_priv {
649 char name[MLX5_MAX_NAME_LEN];
650 struct mlx5_eq_table eq_table;
651 struct mlx5_irq_info *irq_info;
652
653 /* pages stuff */
654 struct workqueue_struct *pg_wq;
655 struct rb_root page_root;
656 int fw_pages;
657 atomic_t reg_pages;
658 struct list_head free_list;
659 int vfs_pages;
660
661 struct mlx5_core_health health;
662
663 struct mlx5_srq_table srq_table;
664
665 /* start: qp staff */
666 struct mlx5_qp_table qp_table;
667 struct dentry *qp_debugfs;
668 struct dentry *eq_debugfs;
669 struct dentry *cq_debugfs;
670 struct dentry *cmdif_debugfs;
671 /* end: qp staff */
672
673 /* start: mkey staff */
674 struct mlx5_mkey_table mkey_table;
675 /* end: mkey staff */
676
677 /* start: alloc staff */
678 /* protect buffer alocation according to numa node */
679 struct mutex alloc_mutex;
680 int numa_node;
681
682 struct mutex pgdir_mutex;
683 struct list_head pgdir_list;
684 /* end: alloc staff */
685 struct dentry *dbg_root;
686
687 /* protect mkey key part */
688 spinlock_t mkey_lock;
689 u8 mkey_key;
690
691 struct list_head dev_list;
692 struct list_head ctx_list;
693 spinlock_t ctx_lock;
694
695 struct list_head waiting_events_list;
696 bool is_accum_events;
697
698 struct mlx5_flow_steering *steering;
699 struct mlx5_mpfs *mpfs;
700 struct mlx5_eswitch *eswitch;
701 struct mlx5_core_sriov sriov;
702 struct mlx5_lag *lag;
703 unsigned long pci_dev_data;
704 struct mlx5_fc_stats fc_stats;
705 struct mlx5_rl_table rl_table;
706
707 struct mlx5_port_module_event_stats pme_stats;
708
709 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
710 void (*pfault)(struct mlx5_core_dev *dev,
711 void *context,
712 struct mlx5_pagefault *pfault);
713 void *pfault_ctx;
714 struct srcu_struct pfault_srcu;
715 #endif
716 struct mlx5_bfreg_data bfregs;
717 struct mlx5_uars_page *uar;
718 };
719
720 enum mlx5_device_state {
721 MLX5_DEVICE_STATE_UP,
722 MLX5_DEVICE_STATE_INTERNAL_ERROR,
723 };
724
725 enum mlx5_interface_state {
726 MLX5_INTERFACE_STATE_UP = BIT(0),
727 };
728
729 enum mlx5_pci_status {
730 MLX5_PCI_STATUS_DISABLED,
731 MLX5_PCI_STATUS_ENABLED,
732 };
733
734 enum mlx5_pagefault_type_flags {
735 MLX5_PFAULT_REQUESTOR = 1 << 0,
736 MLX5_PFAULT_WRITE = 1 << 1,
737 MLX5_PFAULT_RDMA = 1 << 2,
738 };
739
740 /* Contains the details of a pagefault. */
741 struct mlx5_pagefault {
742 u32 bytes_committed;
743 u32 token;
744 u8 event_subtype;
745 u8 type;
746 union {
747 /* Initiator or send message responder pagefault details. */
748 struct {
749 /* Received packet size, only valid for responders. */
750 u32 packet_size;
751 /*
752 * Number of resource holding WQE, depends on type.
753 */
754 u32 wq_num;
755 /*
756 * WQE index. Refers to either the send queue or
757 * receive queue, according to event_subtype.
758 */
759 u16 wqe_index;
760 } wqe;
761 /* RDMA responder pagefault details */
762 struct {
763 u32 r_key;
764 /*
765 * Received packet size, minimal size page fault
766 * resolution required for forward progress.
767 */
768 u32 packet_size;
769 u32 rdma_op_len;
770 u64 rdma_va;
771 } rdma;
772 };
773
774 struct mlx5_eq *eq;
775 struct work_struct work;
776 };
777
778 struct mlx5_td {
779 struct list_head tirs_list;
780 u32 tdn;
781 };
782
783 struct mlx5e_resources {
784 u32 pdn;
785 struct mlx5_td td;
786 struct mlx5_core_mkey mkey;
787 struct mlx5_sq_bfreg bfreg;
788 };
789
790 #define MLX5_MAX_RESERVED_GIDS 8
791
792 struct mlx5_rsvd_gids {
793 unsigned int start;
794 unsigned int count;
795 struct ida ida;
796 };
797
798 #define MAX_PIN_NUM 8
799 struct mlx5_pps {
800 u8 pin_caps[MAX_PIN_NUM];
801 struct work_struct out_work;
802 u64 start[MAX_PIN_NUM];
803 u8 enabled;
804 };
805
806 struct mlx5_clock {
807 rwlock_t lock;
808 struct cyclecounter cycles;
809 struct timecounter tc;
810 struct hwtstamp_config hwtstamp_config;
811 u32 nominal_c_mult;
812 unsigned long overflow_period;
813 struct delayed_work overflow_work;
814 struct mlx5_core_dev *mdev;
815 struct ptp_clock *ptp;
816 struct ptp_clock_info ptp_info;
817 struct mlx5_pps pps_info;
818 };
819
820 struct mlx5_fw_tracer;
821 struct mlx5_vxlan;
822
823 struct mlx5_core_dev {
824 struct pci_dev *pdev;
825 /* sync pci state */
826 struct mutex pci_status_mutex;
827 enum mlx5_pci_status pci_status;
828 u8 rev_id;
829 char board_id[MLX5_BOARD_ID_LEN];
830 struct mlx5_cmd cmd;
831 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
832 struct {
833 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
834 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
835 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
836 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
837 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
838 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
839 } caps;
840 phys_addr_t iseg_base;
841 struct mlx5_init_seg __iomem *iseg;
842 enum mlx5_device_state state;
843 /* sync interface state */
844 struct mutex intf_state_mutex;
845 unsigned long intf_state;
846 void (*event) (struct mlx5_core_dev *dev,
847 enum mlx5_dev_event event,
848 unsigned long param);
849 struct mlx5_priv priv;
850 struct mlx5_profile *profile;
851 atomic_t num_qps;
852 u32 issi;
853 struct mlx5e_resources mlx5e_res;
854 struct mlx5_vxlan *vxlan;
855 struct {
856 struct mlx5_rsvd_gids reserved_gids;
857 u32 roce_en;
858 } roce;
859 #ifdef CONFIG_MLX5_FPGA
860 struct mlx5_fpga_device *fpga;
861 #endif
862 #ifdef CONFIG_RFS_ACCEL
863 struct cpu_rmap *rmap;
864 #endif
865 struct mlx5_clock clock;
866 struct mlx5_ib_clock_info *clock_info;
867 struct page *clock_info_page;
868 struct mlx5_fw_tracer *tracer;
869 };
870
871 struct mlx5_db {
872 __be32 *db;
873 union {
874 struct mlx5_db_pgdir *pgdir;
875 struct mlx5_ib_user_db_page *user_page;
876 } u;
877 dma_addr_t dma;
878 int index;
879 };
880
881 enum {
882 MLX5_COMP_EQ_SIZE = 1024,
883 };
884
885 enum {
886 MLX5_PTYS_IB = 1 << 0,
887 MLX5_PTYS_EN = 1 << 2,
888 };
889
890 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
891
892 enum {
893 MLX5_CMD_ENT_STATE_PENDING_COMP,
894 };
895
896 struct mlx5_cmd_work_ent {
897 unsigned long state;
898 struct mlx5_cmd_msg *in;
899 struct mlx5_cmd_msg *out;
900 void *uout;
901 int uout_size;
902 mlx5_cmd_cbk_t callback;
903 struct delayed_work cb_timeout_work;
904 void *context;
905 int idx;
906 struct completion done;
907 struct mlx5_cmd *cmd;
908 struct work_struct work;
909 struct mlx5_cmd_layout *lay;
910 int ret;
911 int page_queue;
912 u8 status;
913 u8 token;
914 u64 ts1;
915 u64 ts2;
916 u16 op;
917 bool polling;
918 };
919
920 struct mlx5_pas {
921 u64 pa;
922 u8 log_sz;
923 };
924
925 enum phy_port_state {
926 MLX5_AAA_111
927 };
928
929 struct mlx5_hca_vport_context {
930 u32 field_select;
931 bool sm_virt_aware;
932 bool has_smi;
933 bool has_raw;
934 enum port_state_policy policy;
935 enum phy_port_state phys_state;
936 enum ib_port_state vport_state;
937 u8 port_physical_state;
938 u64 sys_image_guid;
939 u64 port_guid;
940 u64 node_guid;
941 u32 cap_mask1;
942 u32 cap_mask1_perm;
943 u32 cap_mask2;
944 u32 cap_mask2_perm;
945 u16 lid;
946 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
947 u8 lmc;
948 u8 subnet_timeout;
949 u16 sm_lid;
950 u8 sm_sl;
951 u16 qkey_violation_counter;
952 u16 pkey_violation_counter;
953 bool grh_required;
954 };
955
mlx5_buf_offset(struct mlx5_frag_buf * buf,int offset)956 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
957 {
958 return buf->frags->buf + offset;
959 }
960
961 #define STRUCT_FIELD(header, field) \
962 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
963 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
964
pci2mlx5_core_dev(struct pci_dev * pdev)965 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
966 {
967 return pci_get_drvdata(pdev);
968 }
969
970 extern struct dentry *mlx5_debugfs_root;
971
fw_rev_maj(struct mlx5_core_dev * dev)972 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
973 {
974 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
975 }
976
fw_rev_min(struct mlx5_core_dev * dev)977 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
978 {
979 return ioread32be(&dev->iseg->fw_rev) >> 16;
980 }
981
fw_rev_sub(struct mlx5_core_dev * dev)982 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
983 {
984 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
985 }
986
cmdif_rev(struct mlx5_core_dev * dev)987 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
988 {
989 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
990 }
991
mlx5_base_mkey(const u32 key)992 static inline u32 mlx5_base_mkey(const u32 key)
993 {
994 return key & 0xffffff00u;
995 }
996
mlx5_fill_fbc_offset(u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)997 static inline void mlx5_fill_fbc_offset(u8 log_stride, u8 log_sz,
998 u16 strides_offset,
999 struct mlx5_frag_buf_ctrl *fbc)
1000 {
1001 fbc->log_stride = log_stride;
1002 fbc->log_sz = log_sz;
1003 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
1004 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
1005 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
1006 fbc->strides_offset = strides_offset;
1007 }
1008
mlx5_fill_fbc(u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)1009 static inline void mlx5_fill_fbc(u8 log_stride, u8 log_sz,
1010 struct mlx5_frag_buf_ctrl *fbc)
1011 {
1012 mlx5_fill_fbc_offset(log_stride, log_sz, 0, fbc);
1013 }
1014
mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl * fbc,void * cqc)1015 static inline void mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl *fbc,
1016 void *cqc)
1017 {
1018 mlx5_fill_fbc(6 + MLX5_GET(cqc, cqc, cqe_sz),
1019 MLX5_GET(cqc, cqc, log_cq_size),
1020 fbc);
1021 }
1022
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)1023 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
1024 u32 ix)
1025 {
1026 unsigned int frag;
1027
1028 ix += fbc->strides_offset;
1029 frag = ix >> fbc->log_frag_strides;
1030
1031 return fbc->frag_buf.frags[frag].buf +
1032 ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
1033 }
1034
1035 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)1036 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
1037 {
1038 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
1039
1040 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
1041 }
1042
1043 int mlx5_cmd_init(struct mlx5_core_dev *dev);
1044 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
1045 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
1046 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
1047
1048 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1049 int out_size);
1050 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1051 void *out, int out_size, mlx5_cmd_cbk_t callback,
1052 void *context);
1053 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1054 void *out, int out_size);
1055 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
1056
1057 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1058 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
1059 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
1060 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1061 int mlx5_health_init(struct mlx5_core_dev *dev);
1062 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1063 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1064 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1065 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1066 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
1067 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1068 struct mlx5_frag_buf *buf, int node);
1069 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
1070 int size, struct mlx5_frag_buf *buf);
1071 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1072 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1073 struct mlx5_frag_buf *buf, int node);
1074 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1075 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1076 gfp_t flags, int npages);
1077 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1078 struct mlx5_cmd_mailbox *head);
1079 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1080 struct mlx5_srq_attr *in);
1081 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
1082 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1083 struct mlx5_srq_attr *out);
1084 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1085 u16 lwm, int is_srq);
1086 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
1087 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
1088 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1089 struct mlx5_core_mkey *mkey,
1090 u32 *in, int inlen,
1091 u32 *out, int outlen,
1092 mlx5_cmd_cbk_t callback, void *context);
1093 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1094 struct mlx5_core_mkey *mkey,
1095 u32 *in, int inlen);
1096 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
1097 struct mlx5_core_mkey *mkey);
1098 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
1099 u32 *out, int outlen);
1100 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1101 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1102 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1103 u16 opmod, u8 port);
1104 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1105 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1106 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1107 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1108 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1109 s32 npages);
1110 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1111 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1112 void mlx5_register_debugfs(void);
1113 void mlx5_unregister_debugfs(void);
1114
1115 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
1116 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1117 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1118 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1119 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1120 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1121 unsigned int *irqn);
1122 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1123 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1124
1125 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1126 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1127 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1128 int size_in, void *data_out, int size_out,
1129 u16 reg_num, int arg, int write);
1130
1131 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1132 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1133 int node);
1134 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1135
1136 const char *mlx5_command_str(int command);
1137 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1138 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1139 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1140 int npsvs, u32 *sig_index);
1141 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1142 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1143 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1144 struct mlx5_odp_caps *odp_caps);
1145 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1146 u8 port_num, void *out, size_t sz);
1147 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1148 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1149 u32 wq_num, u8 type, int error);
1150 #endif
1151
1152 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1153 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1154 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1155 struct mlx5_rate_limit *rl);
1156 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1157 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1158 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1159 struct mlx5_rate_limit *rl_1);
1160 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1161 bool map_wc, bool fast_path);
1162 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1163
1164 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1165 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1166 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1167 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1168
fw_initializing(struct mlx5_core_dev * dev)1169 static inline int fw_initializing(struct mlx5_core_dev *dev)
1170 {
1171 return ioread32be(&dev->iseg->initializing) >> 31;
1172 }
1173
mlx5_mkey_to_idx(u32 mkey)1174 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1175 {
1176 return mkey >> 8;
1177 }
1178
mlx5_idx_to_mkey(u32 mkey_idx)1179 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1180 {
1181 return mkey_idx << 8;
1182 }
1183
mlx5_mkey_variant(u32 mkey)1184 static inline u8 mlx5_mkey_variant(u32 mkey)
1185 {
1186 return mkey & 0xff;
1187 }
1188
1189 enum {
1190 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1191 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1192 };
1193
1194 enum {
1195 MR_CACHE_LAST_STD_ENTRY = 20,
1196 MLX5_IMR_MTT_CACHE_ENTRY,
1197 MLX5_IMR_KSM_CACHE_ENTRY,
1198 MAX_MR_CACHE_ENTRIES
1199 };
1200
1201 enum {
1202 MLX5_INTERFACE_PROTOCOL_IB = 0,
1203 MLX5_INTERFACE_PROTOCOL_ETH = 1,
1204 };
1205
1206 struct mlx5_interface {
1207 void * (*add)(struct mlx5_core_dev *dev);
1208 void (*remove)(struct mlx5_core_dev *dev, void *context);
1209 int (*attach)(struct mlx5_core_dev *dev, void *context);
1210 void (*detach)(struct mlx5_core_dev *dev, void *context);
1211 void (*event)(struct mlx5_core_dev *dev, void *context,
1212 enum mlx5_dev_event event, unsigned long param);
1213 void (*pfault)(struct mlx5_core_dev *dev,
1214 void *context,
1215 struct mlx5_pagefault *pfault);
1216 void * (*get_dev)(void *context);
1217 int protocol;
1218 struct list_head list;
1219 };
1220
1221 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1222 int mlx5_register_interface(struct mlx5_interface *intf);
1223 void mlx5_unregister_interface(struct mlx5_interface *intf);
1224 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1225
1226 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1227 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1228 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1229 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1230 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1231 u64 *values,
1232 int num_counters,
1233 size_t *offsets);
1234 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1235 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1236
1237 #ifndef CONFIG_MLX5_CORE_IPOIB
1238 static inline
mlx5_rdma_netdev_alloc(struct mlx5_core_dev * mdev,struct ib_device * ibdev,const char * name,void (* setup)(struct net_device *))1239 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1240 struct ib_device *ibdev,
1241 const char *name,
1242 void (*setup)(struct net_device *))
1243 {
1244 return ERR_PTR(-EOPNOTSUPP);
1245 }
1246 #else
1247 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1248 struct ib_device *ibdev,
1249 const char *name,
1250 void (*setup)(struct net_device *));
1251 #endif /* CONFIG_MLX5_CORE_IPOIB */
1252
1253 struct mlx5_profile {
1254 u64 mask;
1255 u8 log_max_qp;
1256 struct {
1257 int size;
1258 int limit;
1259 } mr_cache[MAX_MR_CACHE_ENTRIES];
1260 };
1261
1262 enum {
1263 MLX5_PCI_DEV_IS_VF = 1 << 0,
1264 };
1265
mlx5_core_is_pf(struct mlx5_core_dev * dev)1266 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1267 {
1268 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1269 }
1270
1271 #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev))
1272 #define MLX5_VPORT_MANAGER(mdev) \
1273 (MLX5_CAP_GEN(mdev, vport_group_manager) && \
1274 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \
1275 mlx5_core_is_pf(mdev))
1276
mlx5_get_gid_table_len(u16 param)1277 static inline int mlx5_get_gid_table_len(u16 param)
1278 {
1279 if (param > 4) {
1280 pr_warn("gid table length is zero\n");
1281 return 0;
1282 }
1283
1284 return 8 * (1 << param);
1285 }
1286
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1287 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1288 {
1289 return !!(dev->priv.rl_table.max_size);
1290 }
1291
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1292 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1293 {
1294 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1295 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1296 }
1297
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1298 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1299 {
1300 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1301 }
1302
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1303 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1304 {
1305 return mlx5_core_is_mp_slave(dev) ||
1306 mlx5_core_is_mp_master(dev);
1307 }
1308
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1309 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1310 {
1311 if (!mlx5_core_mp_enabled(dev))
1312 return 1;
1313
1314 return MLX5_CAP_GEN(dev, native_port_num);
1315 }
1316
1317 enum {
1318 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1319 };
1320
1321 static inline const struct cpumask *
mlx5_get_vector_affinity_hint(struct mlx5_core_dev * dev,int vector)1322 mlx5_get_vector_affinity_hint(struct mlx5_core_dev *dev, int vector)
1323 {
1324 return dev->priv.irq_info[vector].mask;
1325 }
1326
1327 #endif /* MLX5_DRIVER_H */
1328
