Searched refs:MI_LOAD_REGISTER_IMM (Results 1 – 9 of 9) sorted by relevance
293 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES); in emit_mocs_control_table()351 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2); in emit_mocs_l3cc_table()
123 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) macro
683 *cs++ = MI_LOAD_REGISTER_IMM(1); in gen6_signal()1493 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()1497 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()1566 *cs++ = MI_LOAD_REGISTER_IMM(num_rings); in mi_set_context()1613 *cs++ = MI_LOAD_REGISTER_IMM(num_rings); in mi_set_context()1655 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); in remap_l3()
1433 *batch++ = MI_LOAD_REGISTER_IMM(1); in gen8_emit_flush_coherentl3_wa()1508 *batch++ = MI_LOAD_REGISTER_IMM(count); in emit_lri()2004 *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds); in intel_logical_ring_emit_pdps()2583 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | in execlists_init_reg_state()2629 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; in execlists_init_reg_state()2651 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); in execlists_init_reg_state()
223 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,1185 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) && in check_cmd()
567 *cs++ = MI_LOAD_REGISTER_IMM(w->count); in intel_ctx_workarounds_emit()
1885 *cs++ = MI_LOAD_REGISTER_IMM(4); in i915_reset_gen7_sol_offsets()
1711 *cs++ = MI_LOAD_REGISTER_IMM(ARRAY_SIZE(flex_mmio) + 1); in gen8_emit_oa_config()
213 *cs++ = MI_LOAD_REGISTER_IMM(count); in restore_context_mmio_for_inhibit()248 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE); in restore_render_mocs_control_for_inhibit()275 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2); in restore_render_mocs_l3cc_for_inhibit()
