Searched refs:MII_ADDR_C45 (Results 1 – 20 of 20) sorted by relevance
16 #define BCM87XX_PMD_RX_SIGNAL_DETECT (MII_ADDR_C45 | 0x1000a)17 #define BCM87XX_10GBASER_PCS_STATUS (MII_ADDR_C45 | 0x30020)18 #define BCM87XX_XGXS_LANE_STATUS (MII_ADDR_C45 | 0x40018)20 #define BCM87XX_LASI_CONTROL (MII_ADDR_C45 | 0x39002)21 #define BCM87XX_LASI_STATUS (MII_ADDR_C45 | 0x39005)61 u32 regnum = MII_ADDR_C45 | (devid << 16) | reg; in bcm87xx_of_reg_init()
73 if (regnum & MII_ADDR_C45) { in cavium_mdiobus_read()114 if (regnum & MII_ADDR_C45) { in cavium_mdiobus_write()
160 if (reg & MII_ADDR_C45) { in mdiobb_read()191 if (reg & MII_ADDR_C45) { in mdiobb_write()
30 MII_ADDR_C45 | regnum); in cortina_read_reg()
268 u32 addr = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff); in phy_read_mmd()306 u32 addr = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff); in phy_write_mmd()
482 reg_addr = MII_ADDR_C45 | dev_addr << 16 | MDIO_DEVS2; in get_phy_c45_devs_in_pkg()488 reg_addr = MII_ADDR_C45 | dev_addr << 16 | MDIO_DEVS1; in get_phy_c45_devs_in_pkg()549 reg_addr = MII_ADDR_C45 | i << 16 | MII_PHYSID1; in get_phy_c45_ids()555 reg_addr = MII_ADDR_C45 | i << 16 | MII_PHYSID2; in get_phy_c45_ids()
1372 devad = MII_ADDR_C45 | devad << 16 | reg; in phylink_phy_read()1395 devad = MII_ADDR_C45 | devad << 16 | reg; in phylink_phy_read()1412 devad = MII_ADDR_C45 | devad << 16 | reg; in phylink_phy_write()1435 devad = MII_ADDR_C45 | devad << 16 | reg; in phylink_phy_write()
132 if (reg & MII_ADDR_C45) in start_miim_ops()
138 if (regnum & MII_ADDR_C45) { in xgmac_mdio_write()159 if (regnum & MII_ADDR_C45) { in xgmac_mdio_write()194 if (regnum & MII_ADDR_C45) { in xgmac_mdio_read()213 if (regnum & MII_ADDR_C45) { in xgmac_mdio_read()
147 if (regnum & MII_ADDR_C45) in orion_mdio_smi_read()178 if (regnum & MII_ADDR_C45) in orion_mdio_smi_write()212 if (!(regnum & MII_ADDR_C45)) in orion_mdio_xsmi_read()245 if (!(regnum & MII_ADDR_C45)) in orion_mdio_xsmi_write()
85 if (phyreg & MII_ADDR_C45) { in stmmac_xgmac2_mdio_read()125 if (phyreg & MII_ADDR_C45) { in stmmac_xgmac2_mdio_write()
227 u8 is_c45 = !!(regnum & MII_ADDR_C45); in hns_mdio_write()289 u8 is_c45 = !!(regnum & MII_ADDR_C45); in hns_mdio_read()
43 int reg_c45 = MII_ADDR_C45 | device << 16 | reg; in mv88e6390_serdes_read()51 int reg_c45 = MII_ADDR_C45 | device << 16 | reg; in mv88e6390_serdes_write()
759 if (reg & MII_ADDR_C45) in mv88e6xxx_g2_smi_phy_read()773 if (reg & MII_ADDR_C45) in mv88e6xxx_g2_smi_phy_write()
92 if (phyreg & MII_ADDR_C45) { in sxgbe_mdio_access()
1150 if (mmd_reg & MII_ADDR_C45) in xgbe_read_mmd_regs_v2()1151 mmd_address = mmd_reg & ~MII_ADDR_C45; in xgbe_read_mmd_regs_v2()1182 if (mmd_reg & MII_ADDR_C45) in xgbe_write_mmd_regs_v2()1183 mmd_address = mmd_reg & ~MII_ADDR_C45; in xgbe_write_mmd_regs_v2()1213 if (mmd_reg & MII_ADDR_C45) in xgbe_read_mmd_regs_v1()1214 mmd_address = mmd_reg & ~MII_ADDR_C45; in xgbe_read_mmd_regs_v1()1241 if (mmd_reg & MII_ADDR_C45) in xgbe_write_mmd_regs_v1()1242 mmd_address = mmd_reg & ~MII_ADDR_C45; in xgbe_write_mmd_regs_v1()
1686 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff)))1693 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val)))
605 if (reg & MII_ADDR_C45) { in xgbe_phy_mdio_mii_write()665 if (reg & MII_ADDR_C45) { in xgbe_phy_mdio_mii_read()
1036 if (reg & MII_ADDR_C45) { in nixge_mdio_read()1085 if (reg & MII_ADDR_C45) { in nixge_mdio_write()
183 #define MII_ADDR_C45 (1<<30) macro
