Searched refs:MIC_X100_SBOX_BASE_ADDRESS (Results 1 – 4 of 4) sorted by relevance
49 MIC_X100_SBOX_BASE_ADDRESS + in mic_x100_write_spad()66 MIC_X100_SBOX_BASE_ADDRESS + in mic_x100_read_spad()82 u32 sice0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SICE0; in mic_x100_enable_interrupts()83 u32 siac0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SIAC0; in mic_x100_enable_interrupts()109 u32 sice0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SICE0; in mic_x100_disable_interrupts()110 u32 siac0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SIAC0; in mic_x100_disable_interrupts()111 u32 sicc0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SICC0; in mic_x100_disable_interrupts()133 u32 apicicr_low = mic_mmio_read(mw, MIC_X100_SBOX_BASE_ADDRESS + in mic_x100_send_sbox_intr()142 MIC_X100_SBOX_BASE_ADDRESS + apic_icr_offset); in mic_x100_send_sbox_intr()156 MIC_X100_SBOX_BASE_ADDRESS + rdmasr_offset); in mic_x100_send_rdmasr_intr()[all …]
43 #define MIC_X100_SBOX_BASE_ADDRESS 0x00010000 macro
51 MIC_X100_SBOX_BASE_ADDRESS + in mic_read_spad()69 MIC_X100_SBOX_BASE_ADDRESS + in mic_send_intr()79 u32 apicicr_low = mic_mmio_read(mw, MIC_X100_SBOX_BASE_ADDRESS + in mic_x100_send_sbox_intr()92 MIC_X100_SBOX_BASE_ADDRESS + apic_icr_offset); in mic_x100_send_sbox_intr()105 mic_mmio_write(mw, 0, MIC_X100_SBOX_BASE_ADDRESS + rdmasr_offset); in mic_x100_send_rdmasr_intr()
32 #define MIC_X100_SBOX_BASE_ADDRESS 0x00010000ULL macro
