Searched refs:MG_PLL_DIV0 (Results 1 – 2 of 2) sorted by relevance
2966 hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(port)); in icl_pll_get_hw_state()3039 I915_WRITE(MG_PLL_DIV0(port), hw_state->mg_pll_div0); in icl_mg_pll_write()
9385 #define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \ macro
