Searched refs:MDIO_START (Results 1 – 7 of 7) sorted by relevance
34 #define MDIO_START BIT(23) macro63 MDIO_START | MDIO_RD_NWR; in emac_mdio_read()68 !(reg & (MDIO_START | MDIO_BUSY)), in emac_mdio_read()87 MDIO_START; in emac_mdio_write()92 !(reg & (MDIO_START | MDIO_BUSY)), in emac_mdio_write()
219 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | in atl1e_read_phy_reg()229 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1e_read_phy_reg()233 if (!(val & (MDIO_START | MDIO_BUSY))) { in atl1e_read_phy_reg()255 MDIO_START | in atl1e_write_phy_reg()264 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1e_write_phy_reg()269 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1e_write_phy_reg()405 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1e_phy_commit()409 if (0 != (val & (MDIO_START | MDIO_BUSY))) { in atl1e_phy_commit()
236 #define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this … macro
2514 MDIO_START | in atl2_read_phy_reg()2525 if (!(val & (MDIO_START | MDIO_BUSY))) in atl2_read_phy_reg()2529 if (!(val & (MDIO_START | MDIO_BUSY))) { in atl2_read_phy_reg()2551 MDIO_START | in atl2_write_phy_reg()2560 if (!(val & (MDIO_START | MDIO_BUSY))) in atl2_write_phy_reg()2566 if (!(val & (MDIO_START | MDIO_BUSY))) in atl2_write_phy_reg()2664 if (!(val & (MDIO_START | MDIO_BUSY))) in atl2_phy_commit()2668 if (0 != (val & (MDIO_START | MDIO_BUSY))) { in atl2_phy_commit()
176 #define MDIO_START 0x800000 macro
365 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 << in atl1_read_phy_reg()373 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1_read_phy_reg()376 if (!(val & (MDIO_START | MDIO_BUSY))) { in atl1_read_phy_reg()614 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; in atl1_write_phy_reg()621 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1_write_phy_reg()625 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1_write_phy_reg()694 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1_phy_reset()698 if ((val & (MDIO_START | MDIO_BUSY)) != 0) { in atl1_phy_reset()
51 #define MDIO_START BIT(20) macro53 #define MDIO_READ (BIT(17) | MDIO_START)54 #define MDIO_WRITE (BIT(16) | MDIO_START)927 for (i = 0; readl_relaxed(base + MDIO_SINGLE_CMD) & MDIO_START; i++) { in hix5hd2_mdio_wait_ready()
