Searched refs:MCR_RTS (Results 1 – 9 of 9) sorted by relevance
66 #define MCR_RTS 0x02 macro313 priv->line_control |= MCR_RTS; in spcp8x5_set_termios()427 priv->line_control |= MCR_RTS; in spcp8x5_tiocmset()431 priv->line_control &= ~MCR_RTS; in spcp8x5_tiocmset()458 | ((mcr & MCR_RTS) ? TIOCM_RTS : 0) in spcp8x5_tiocmget()
123 #define MCR_RTS 0x02 // Assert RTS macro
52 #define MCR_RTS 0x02 /* Assert RTS */ macro1422 mos7840_port->shadowMCR &= ~MCR_RTS; in mos7840_throttle()1463 mos7840_port->shadowMCR |= MCR_RTS; in mos7840_unthrottle()1491 | ((mcr & MCR_RTS) ? TIOCM_RTS : 0) in mos7840_tiocmget()1519 mcr &= ~MCR_RTS; in mos7840_tiocmset()1526 mcr |= MCR_RTS; in mos7840_tiocmset()1812 mos7840_port->shadowMCR |= (MCR_DTR | MCR_RTS); in mos7840_change_port_settings()
1528 status = ti_do_config(port, UMPC_SET_CLR_RTS, mcr & MCR_RTS); in restore_mcr()1924 edge_port->shadow_mcr = MCR_RTS | MCR_DTR; in edge_open()2203 edge_port->shadow_mcr &= ~MCR_RTS; in stop_read()2221 edge_port->shadow_mcr |= MCR_RTS; in restart_read()2393 mcr |= MCR_RTS; in edge_tiocmset()2400 mcr &= ~MCR_RTS; in edge_tiocmset()2427 | ((mcr & MCR_RTS) ? TIOCM_RTS: 0) /* 0x004 */ in edge_tiocmget()
1495 edge_port->shadowMCR &= ~MCR_RTS; in edge_throttle()1532 edge_port->shadowMCR |= MCR_RTS; in edge_unthrottle()1600 mcr |= MCR_RTS; in edge_tiocmset()1607 mcr &= ~MCR_RTS; in edge_tiocmset()1631 | ((mcr & MCR_RTS) ? TIOCM_RTS: 0) /* 0x004 */ in edge_tiocmget()2601 edge_port->shadowMCR |= (MCR_DTR | MCR_RTS); in change_port_settings()
132 #define MCR_RTS 0x0200 /* Request to Send */ macro
123 #define MCR_RTS (1 << 1) /* Request to Send */ macro
73 #define MCR_RTS 0x02 macro
197 #define MCR_RTS 0x02 /* RTS output */ macro240 #define PTT_ON (MCR_RTS|MCR_OUT2) /* activate PTT */320 outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase)); in fpga_reset()335 bit = (wrd & 0x80) ? (MCR_RTS | MCR_DTR) : MCR_DTR; in fpga_write()
