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Searched refs:MCLK (Results 1 – 25 of 32) sorted by relevance

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/Linux-v4.19/Documentation/devicetree/bindings/sound/
Dmt8173-rt5650.txt16 - mediatek,mclk: the MCLK source
17 0 : external oscillator, MCLK = 12.288M
18 1 : internal source from mt8173, MCLK = sampling rate*256
Dcs42l56.txt20 Frequency = MCLK / 4 * (N+2)
22 MCLK = Where MCLK is the frequency of the mclk signal after the MCLKDIV2 circuit.
Dtas2552.txt18 tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
Dmax9860.txt14 - clocks : A clock specifier for the clock connected as MCLK.
Dda7213.txt10 - clocks : phandle and clock specifier for codec MCLK.
Dcs4271.txt24 The CS4271 requires its LRCLK and MCLK to be stable before its RESET
Dtas571x.txt22 - clocks: clock phandle for the MCLK input
Dcs43130.txt20 When external MCLK is generated by external crystal
Domap-abe-twl6040.txt6 - ti,mclk-freq: MCLK frequency for HPPLL operation
Dnau8825.txt76 - clock-names: should include "mclk" for the MCLK master clock
Dda7218.txt25 - clocks : phandle and clock specifier for codec MCLK.
Dfsl-sai.txt56 indicates that SAI will output the SAI MCLK clock.
Dda7219.txt29 - clocks : phandle and clock specifier for codec MCLK.
/Linux-v4.19/Documentation/devicetree/bindings/media/
Dpxa-camera.txt12 sensor master clock MCLK
13 - clock-frequency: host interface is driving MCLK, and MCLK rate is this rate
/Linux-v4.19/Documentation/sound/soc/
Dclocking.rst12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
34 - BCLK = MCLK / x, or
/Linux-v4.19/arch/arm/mach-ebsa110/
Dcore.c144 #define MCLK 47894000 macro
149 #define CLKBY7 (MCLK / 7)
/Linux-v4.19/drivers/spi/
Dspi-mpc52xx-psc.c31 #define MCLK 20000000 /* PSC port MClk in hz */ macro
108 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
110 ccr |= (MCLK / 1000000 - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
320 mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK; in mpc52xx_psc_spi_port_config()
/Linux-v4.19/drivers/media/pci/ddbridge/
Dddbridge-sx8.c23 static const u32 MCLK = (1550000000 / 12); variable
196 if (p->symbol_rate >= (MCLK / 2)) in start()
218 if (p->symbol_rate >= MCLK / 2) { in start()
253 i = (p->symbol_rate > (MCLK / 2)) ? 3 : 7; in start()
/Linux-v4.19/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.txt23 "core" - SDC MMC clock (MCLK) (required)
/Linux-v4.19/Documentation/devicetree/bindings/mfd/
Dtwl6040.txt23 - clock-names: Must be "clk32k" for the 32K clock and "mclk" for the MCLK.
/Linux-v4.19/arch/arm/mm/
Dproc-sa110.S97 ldr r1, [r1, #0] @ force switch to MCLK
Dproc-sa1100.S112 ldr r1, [r1, #0] @ force switch to MCLK
/Linux-v4.19/drivers/video/fbdev/sis/
Dinit.c2268 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK, in SiS_DoCalcDelay() argument
2281 idx1 = longtemp % (MCLK * 16); in SiS_DoCalcDelay()
2282 longtemp /= (MCLK * 16); in SiS_DoCalcDelay()
2289 unsigned short colordepth, unsigned short MCLK) in SiS_CalcDelay() argument
2293 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0); in SiS_CalcDelay()
2294 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1); in SiS_CalcDelay()
2306 unsigned short temp, index, VCLK, MCLK, colorth; in SiS_SetCRT1FIFO_300() local
2324 MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK; in SiS_SetCRT1FIFO_300()
2330 ThresholdLow = SiS_CalcDelay(SiS_Pr, VCLK, colorth, MCLK) + 1; in SiS_SetCRT1FIFO_300()
/Linux-v4.19/drivers/video/fbdev/matrox/
Dmatroxfb_Ti3026.c204 #define TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX)) argument
/Linux-v4.19/arch/powerpc/boot/dts/fsl/
Dp1022rdk.dts56 /* MCLK source is a stand-alone oscillator */

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