1 /* 2 * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #define MMCIPOWER 0x000 11 #define MCI_PWR_OFF 0x00 12 #define MCI_PWR_UP 0x02 13 #define MCI_PWR_ON 0x03 14 #define MCI_OD (1 << 6) 15 #define MCI_ROD (1 << 7) 16 /* 17 * The ST Micro version does not have ROD and reuse the voltage registers for 18 * direction settings. 19 */ 20 #define MCI_ST_DATA2DIREN (1 << 2) 21 #define MCI_ST_CMDDIREN (1 << 3) 22 #define MCI_ST_DATA0DIREN (1 << 4) 23 #define MCI_ST_DATA31DIREN (1 << 5) 24 #define MCI_ST_FBCLKEN (1 << 7) 25 #define MCI_ST_DATA74DIREN (1 << 8) 26 27 #define MMCICLOCK 0x004 28 #define MCI_CLK_ENABLE (1 << 8) 29 #define MCI_CLK_PWRSAVE (1 << 9) 30 #define MCI_CLK_BYPASS (1 << 10) 31 #define MCI_4BIT_BUS (1 << 11) 32 /* 33 * 8bit wide buses, hardware flow contronl, negative edges and clock inversion 34 * supported in ST Micro U300 and Ux500 versions 35 */ 36 #define MCI_ST_8BIT_BUS (1 << 12) 37 #define MCI_ST_U300_HWFCEN (1 << 13) 38 #define MCI_ST_UX500_NEG_EDGE (1 << 13) 39 #define MCI_ST_UX500_HWFCEN (1 << 14) 40 #define MCI_ST_UX500_CLK_INV (1 << 15) 41 /* Modified PL180 on Versatile Express platform */ 42 #define MCI_ARM_HWFCEN (1 << 12) 43 44 /* Modified on Qualcomm Integrations */ 45 #define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11)) 46 #define MCI_QCOM_CLK_FLOWENA BIT(12) 47 #define MCI_QCOM_CLK_INVERTOUT BIT(13) 48 49 /* select in latch data and command in */ 50 #define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15) 51 #define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15)) 52 53 #define MMCIARGUMENT 0x008 54 55 /* The command register controls the Command Path State Machine (CPSM) */ 56 #define MMCICOMMAND 0x00c 57 #define MCI_CPSM_RESPONSE BIT(6) 58 #define MCI_CPSM_LONGRSP BIT(7) 59 #define MCI_CPSM_INTERRUPT BIT(8) 60 #define MCI_CPSM_PENDING BIT(9) 61 #define MCI_CPSM_ENABLE BIT(10) 62 /* Command register flag extenstions in the ST Micro versions */ 63 #define MCI_CPSM_ST_SDIO_SUSP BIT(11) 64 #define MCI_CPSM_ST_ENCMD_COMPL BIT(12) 65 #define MCI_CPSM_ST_NIEN BIT(13) 66 #define MCI_CPSM_ST_CE_ATACMD BIT(14) 67 /* Command register flag extensions in the Qualcomm versions */ 68 #define MCI_CPSM_QCOM_PROGENA BIT(11) 69 #define MCI_CPSM_QCOM_DATCMD BIT(12) 70 #define MCI_CPSM_QCOM_MCIABORT BIT(13) 71 #define MCI_CPSM_QCOM_CCSENABLE BIT(14) 72 #define MCI_CPSM_QCOM_CCSDISABLE BIT(15) 73 #define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16) 74 #define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21) 75 76 #define MMCIRESPCMD 0x010 77 #define MMCIRESPONSE0 0x014 78 #define MMCIRESPONSE1 0x018 79 #define MMCIRESPONSE2 0x01c 80 #define MMCIRESPONSE3 0x020 81 #define MMCIDATATIMER 0x024 82 #define MMCIDATALENGTH 0x028 83 84 /* The data control register controls the Data Path State Machine (DPSM) */ 85 #define MMCIDATACTRL 0x02c 86 #define MCI_DPSM_ENABLE BIT(0) 87 #define MCI_DPSM_DIRECTION BIT(1) 88 #define MCI_DPSM_MODE BIT(2) 89 #define MCI_DPSM_DMAENABLE BIT(3) 90 #define MCI_DPSM_BLOCKSIZE BIT(4) 91 /* Control register extensions in the ST Micro U300 and Ux500 versions */ 92 #define MCI_DPSM_ST_RWSTART BIT(8) 93 #define MCI_DPSM_ST_RWSTOP BIT(9) 94 #define MCI_DPSM_ST_RWMOD BIT(10) 95 #define MCI_DPSM_ST_SDIOEN BIT(11) 96 /* Control register extensions in the ST Micro Ux500 versions */ 97 #define MCI_DPSM_ST_DMAREQCTL BIT(12) 98 #define MCI_DPSM_ST_DBOOTMODEEN BIT(13) 99 #define MCI_DPSM_ST_BUSYMODE BIT(14) 100 #define MCI_DPSM_ST_DDRMODE BIT(15) 101 /* Control register extensions in the Qualcomm versions */ 102 #define MCI_DPSM_QCOM_DATA_PEND BIT(17) 103 #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20) 104 105 #define MMCIDATACNT 0x030 106 #define MMCISTATUS 0x034 107 #define MCI_CMDCRCFAIL (1 << 0) 108 #define MCI_DATACRCFAIL (1 << 1) 109 #define MCI_CMDTIMEOUT (1 << 2) 110 #define MCI_DATATIMEOUT (1 << 3) 111 #define MCI_TXUNDERRUN (1 << 4) 112 #define MCI_RXOVERRUN (1 << 5) 113 #define MCI_CMDRESPEND (1 << 6) 114 #define MCI_CMDSENT (1 << 7) 115 #define MCI_DATAEND (1 << 8) 116 #define MCI_STARTBITERR (1 << 9) 117 #define MCI_DATABLOCKEND (1 << 10) 118 #define MCI_CMDACTIVE (1 << 11) 119 #define MCI_TXACTIVE (1 << 12) 120 #define MCI_RXACTIVE (1 << 13) 121 #define MCI_TXFIFOHALFEMPTY (1 << 14) 122 #define MCI_RXFIFOHALFFULL (1 << 15) 123 #define MCI_TXFIFOFULL (1 << 16) 124 #define MCI_RXFIFOFULL (1 << 17) 125 #define MCI_TXFIFOEMPTY (1 << 18) 126 #define MCI_RXFIFOEMPTY (1 << 19) 127 #define MCI_TXDATAAVLBL (1 << 20) 128 #define MCI_RXDATAAVLBL (1 << 21) 129 /* Extended status bits for the ST Micro variants */ 130 #define MCI_ST_SDIOIT (1 << 22) 131 #define MCI_ST_CEATAEND (1 << 23) 132 #define MCI_ST_CARDBUSY (1 << 24) 133 134 #define MMCICLEAR 0x038 135 #define MCI_CMDCRCFAILCLR (1 << 0) 136 #define MCI_DATACRCFAILCLR (1 << 1) 137 #define MCI_CMDTIMEOUTCLR (1 << 2) 138 #define MCI_DATATIMEOUTCLR (1 << 3) 139 #define MCI_TXUNDERRUNCLR (1 << 4) 140 #define MCI_RXOVERRUNCLR (1 << 5) 141 #define MCI_CMDRESPENDCLR (1 << 6) 142 #define MCI_CMDSENTCLR (1 << 7) 143 #define MCI_DATAENDCLR (1 << 8) 144 #define MCI_STARTBITERRCLR (1 << 9) 145 #define MCI_DATABLOCKENDCLR (1 << 10) 146 /* Extended status bits for the ST Micro variants */ 147 #define MCI_ST_SDIOITC (1 << 22) 148 #define MCI_ST_CEATAENDC (1 << 23) 149 #define MCI_ST_BUSYENDC (1 << 24) 150 151 #define MMCIMASK0 0x03c 152 #define MCI_CMDCRCFAILMASK (1 << 0) 153 #define MCI_DATACRCFAILMASK (1 << 1) 154 #define MCI_CMDTIMEOUTMASK (1 << 2) 155 #define MCI_DATATIMEOUTMASK (1 << 3) 156 #define MCI_TXUNDERRUNMASK (1 << 4) 157 #define MCI_RXOVERRUNMASK (1 << 5) 158 #define MCI_CMDRESPENDMASK (1 << 6) 159 #define MCI_CMDSENTMASK (1 << 7) 160 #define MCI_DATAENDMASK (1 << 8) 161 #define MCI_STARTBITERRMASK (1 << 9) 162 #define MCI_DATABLOCKENDMASK (1 << 10) 163 #define MCI_CMDACTIVEMASK (1 << 11) 164 #define MCI_TXACTIVEMASK (1 << 12) 165 #define MCI_RXACTIVEMASK (1 << 13) 166 #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 167 #define MCI_RXFIFOHALFFULLMASK (1 << 15) 168 #define MCI_TXFIFOFULLMASK (1 << 16) 169 #define MCI_RXFIFOFULLMASK (1 << 17) 170 #define MCI_TXFIFOEMPTYMASK (1 << 18) 171 #define MCI_RXFIFOEMPTYMASK (1 << 19) 172 #define MCI_TXDATAAVLBLMASK (1 << 20) 173 #define MCI_RXDATAAVLBLMASK (1 << 21) 174 /* Extended status bits for the ST Micro variants */ 175 #define MCI_ST_SDIOITMASK (1 << 22) 176 #define MCI_ST_CEATAENDMASK (1 << 23) 177 #define MCI_ST_BUSYENDMASK (1 << 24) 178 179 #define MMCIMASK1 0x040 180 #define MMCIFIFOCNT 0x048 181 #define MMCIFIFO 0x080 /* to 0x0bc */ 182 183 #define MCI_IRQENABLE \ 184 (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ 185 MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ 186 MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK) 187 188 /* These interrupts are directed to IRQ1 when two IRQ lines are available */ 189 #define MCI_IRQ1MASK \ 190 (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ 191 MCI_TXFIFOHALFEMPTYMASK) 192 193 #define NR_SG 128 194 195 #define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain" 196 197 struct clk; 198 struct dma_chan; 199 struct mmci_host; 200 201 /** 202 * struct variant_data - MMCI variant-specific quirks 203 * @clkreg: default value for MCICLOCK register 204 * @clkreg_enable: enable value for MMCICLOCK register 205 * @clkreg_8bit_bus_enable: enable value for 8 bit bus 206 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 207 * @datalength_bits: number of bits in the MMCIDATALENGTH register 208 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 209 * is asserted (likewise for RX) 210 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 211 * is asserted (likewise for RX) 212 * @data_cmd_enable: enable value for data commands. 213 * @st_sdio: enable ST specific SDIO logic 214 * @st_clkdiv: true if using a ST-specific clock divider algorithm 215 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 216 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 217 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl 218 * register 219 * @datactrl_mask_sdio: SDIO enable mask in datactrl register 220 * @pwrreg_powerup: power up value for MMCIPOWER register 221 * @f_max: maximum clk frequency supported by the controller. 222 * @signal_direction: input/out direction of bus signals can be indicated 223 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 224 * @busy_detect: true if the variant supports busy detection on DAT0. 225 * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM 226 * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register 227 * indicating that the card is busy 228 * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for 229 * getting busy end detection interrupts 230 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 231 * @explicit_mclk_control: enable explicit mclk control in driver. 232 * @qcom_fifo: enables qcom specific fifo pio read logic. 233 * @qcom_dml: enables qcom specific dma glue for dma transfers. 234 * @reversed_irq_handling: handle data irq before cmd irq. 235 * @mmcimask1: true if variant have a MMCIMASK1 register. 236 * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS 237 * register. 238 * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register 239 */ 240 struct variant_data { 241 unsigned int clkreg; 242 unsigned int clkreg_enable; 243 unsigned int clkreg_8bit_bus_enable; 244 unsigned int clkreg_neg_edge_enable; 245 unsigned int datalength_bits; 246 unsigned int fifosize; 247 unsigned int fifohalfsize; 248 unsigned int data_cmd_enable; 249 unsigned int datactrl_mask_ddrmode; 250 unsigned int datactrl_mask_sdio; 251 bool st_sdio; 252 bool st_clkdiv; 253 bool blksz_datactrl16; 254 bool blksz_datactrl4; 255 u32 pwrreg_powerup; 256 u32 f_max; 257 bool signal_direction; 258 bool pwrreg_clkgate; 259 bool busy_detect; 260 u32 busy_dpsm_flag; 261 u32 busy_detect_flag; 262 u32 busy_detect_mask; 263 bool pwrreg_nopower; 264 bool explicit_mclk_control; 265 bool qcom_fifo; 266 bool qcom_dml; 267 bool reversed_irq_handling; 268 bool mmcimask1; 269 u32 start_err; 270 u32 opendrain; 271 void (*init)(struct mmci_host *host); 272 }; 273 274 /* mmci variant callbacks */ 275 struct mmci_host_ops { 276 void (*dma_setup)(struct mmci_host *host); 277 }; 278 279 struct mmci_host_next { 280 struct dma_async_tx_descriptor *dma_desc; 281 struct dma_chan *dma_chan; 282 s32 cookie; 283 }; 284 285 struct mmci_host { 286 phys_addr_t phybase; 287 void __iomem *base; 288 struct mmc_request *mrq; 289 struct mmc_command *cmd; 290 struct mmc_data *data; 291 struct mmc_host *mmc; 292 struct clk *clk; 293 bool singleirq; 294 295 spinlock_t lock; 296 297 unsigned int mclk; 298 /* cached value of requested clk in set_ios */ 299 unsigned int clock_cache; 300 unsigned int cclk; 301 u32 pwr_reg; 302 u32 pwr_reg_add; 303 u32 clk_reg; 304 u32 datactrl_reg; 305 u32 busy_status; 306 u32 mask1_reg; 307 bool vqmmc_enabled; 308 struct mmci_platform_data *plat; 309 struct mmci_host_ops *ops; 310 struct variant_data *variant; 311 struct pinctrl *pinctrl; 312 struct pinctrl_state *pins_default; 313 struct pinctrl_state *pins_opendrain; 314 315 u8 hw_designer; 316 u8 hw_revision:4; 317 318 struct timer_list timer; 319 unsigned int oldstat; 320 321 /* pio stuff */ 322 struct sg_mapping_iter sg_miter; 323 unsigned int size; 324 int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain); 325 326 #ifdef CONFIG_DMA_ENGINE 327 /* DMA stuff */ 328 struct dma_chan *dma_current; 329 struct dma_chan *dma_rx_channel; 330 struct dma_chan *dma_tx_channel; 331 struct dma_async_tx_descriptor *dma_desc_current; 332 struct mmci_host_next next_data; 333 bool dma_in_progress; 334 335 #define dma_inprogress(host) ((host)->dma_in_progress) 336 #else 337 #define dma_inprogress(host) (0) 338 #endif 339 }; 340 341
