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Searched refs:MASTER_COMM_CNTL_REG (Results 1 – 5 of 5) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/
Ddce_dmcu.c124 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_set_psr_enable()
137 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_dmcu_set_psr_enable()
221 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_setup_psr()
263 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_dmcu_setup_psr()
298 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); in dce_psr_wait_loop()
309 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_psr_wait_loop()
376 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_get_dmcu_version()
383 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dcn10_get_dmcu_version()
386 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_get_dmcu_version()
416 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_init()
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Ddce_dmcu.h42 SR(MASTER_COMM_CNTL_REG), \
59 SR(MASTER_COMM_CNTL_REG), \
92 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
118 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
172 uint32_t MASTER_COMM_CNTL_REG; member
Ddce_abm.c216 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dmcu_set_backlight_level()
219 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, in dmcu_set_backlight_level()
234 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dmcu_set_backlight_level()
299 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_level()
308 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_abm_set_level()
317 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_immediate_disable()
326 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_abm_immediate_disable()
Ddce_abm.h38 SR(MASTER_COMM_CNTL_REG), \
83 ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
202 uint32_t MASTER_COMM_CNTL_REG; member
Ddce_link_encoder.h122 uint32_t MASTER_COMM_CNTL_REG; member