1 /* 2 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 */ 15 16 #ifndef __MESON_REGISTERS_H 17 #define __MESON_REGISTERS_H 18 19 /* Shift all registers by 2 */ 20 #define _REG(reg) ((reg) << 2) 21 22 #define writel_bits_relaxed(mask, val, addr) \ 23 writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) 24 25 /* vpp2 */ 26 #define VPP2_DUMMY_DATA 0x1900 27 #define VPP2_LINE_IN_LENGTH 0x1901 28 #define VPP2_PIC_IN_HEIGHT 0x1902 29 #define VPP2_SCALE_COEF_IDX 0x1903 30 #define VPP2_SCALE_COEF 0x1904 31 #define VPP2_VSC_REGION12_STARTP 0x1905 32 #define VPP2_VSC_REGION34_STARTP 0x1906 33 #define VPP2_VSC_REGION4_ENDP 0x1907 34 #define VPP2_VSC_START_PHASE_STEP 0x1908 35 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 36 #define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a 37 #define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b 38 #define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c 39 #define VPP2_VSC_PHASE_CTRL 0x190d 40 #define VPP2_VSC_INI_PHASE 0x190e 41 #define VPP2_HSC_REGION12_STARTP 0x1910 42 #define VPP2_HSC_REGION34_STARTP 0x1911 43 #define VPP2_HSC_REGION4_ENDP 0x1912 44 #define VPP2_HSC_START_PHASE_STEP 0x1913 45 #define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914 46 #define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915 47 #define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916 48 #define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917 49 #define VPP2_HSC_PHASE_CTRL 0x1918 50 #define VPP2_SC_MISC 0x1919 51 #define VPP2_PREBLEND_VD1_H_START_END 0x191a 52 #define VPP2_PREBLEND_VD1_V_START_END 0x191b 53 #define VPP2_POSTBLEND_VD1_H_START_END 0x191c 54 #define VPP2_POSTBLEND_VD1_V_START_END 0x191d 55 #define VPP2_PREBLEND_H_SIZE 0x1920 56 #define VPP2_POSTBLEND_H_SIZE 0x1921 57 #define VPP2_HOLD_LINES 0x1922 58 #define VPP2_BLEND_ONECOLOR_CTRL 0x1923 59 #define VPP2_PREBLEND_CURRENT_XY 0x1924 60 #define VPP2_POSTBLEND_CURRENT_XY 0x1925 61 #define VPP2_MISC 0x1926 62 #define VPP2_OFIFO_SIZE 0x1927 63 #define VPP2_FIFO_STATUS 0x1928 64 #define VPP2_SMOKE_CTRL 0x1929 65 #define VPP2_SMOKE1_VAL 0x192a 66 #define VPP2_SMOKE2_VAL 0x192b 67 #define VPP2_SMOKE1_H_START_END 0x192d 68 #define VPP2_SMOKE1_V_START_END 0x192e 69 #define VPP2_SMOKE2_H_START_END 0x192f 70 #define VPP2_SMOKE2_V_START_END 0x1930 71 #define VPP2_SCO_FIFO_CTRL 0x1933 72 #define VPP2_HSC_PHASE_CTRL1 0x1934 73 #define VPP2_HSC_INI_PAT_CTRL 0x1935 74 #define VPP2_VADJ_CTRL 0x1940 75 #define VPP2_VADJ1_Y 0x1941 76 #define VPP2_VADJ1_MA_MB 0x1942 77 #define VPP2_VADJ1_MC_MD 0x1943 78 #define VPP2_VADJ2_Y 0x1944 79 #define VPP2_VADJ2_MA_MB 0x1945 80 #define VPP2_VADJ2_MC_MD 0x1946 81 #define VPP2_MATRIX_PROBE_COLOR 0x195c 82 #define VPP2_MATRIX_HL_COLOR 0x195d 83 #define VPP2_MATRIX_PROBE_POS 0x195e 84 #define VPP2_MATRIX_CTRL 0x195f 85 #define VPP2_MATRIX_COEF00_01 0x1960 86 #define VPP2_MATRIX_COEF02_10 0x1961 87 #define VPP2_MATRIX_COEF11_12 0x1962 88 #define VPP2_MATRIX_COEF20_21 0x1963 89 #define VPP2_MATRIX_COEF22 0x1964 90 #define VPP2_MATRIX_OFFSET0_1 0x1965 91 #define VPP2_MATRIX_OFFSET2 0x1966 92 #define VPP2_MATRIX_PRE_OFFSET0_1 0x1967 93 #define VPP2_MATRIX_PRE_OFFSET2 0x1968 94 #define VPP2_DUMMY_DATA1 0x1969 95 #define VPP2_GAINOFF_CTRL0 0x196a 96 #define VPP2_GAINOFF_CTRL1 0x196b 97 #define VPP2_GAINOFF_CTRL2 0x196c 98 #define VPP2_GAINOFF_CTRL3 0x196d 99 #define VPP2_GAINOFF_CTRL4 0x196e 100 #define VPP2_CHROMA_ADDR_PORT 0x1970 101 #define VPP2_CHROMA_DATA_PORT 0x1971 102 #define VPP2_GCLK_CTRL0 0x1972 103 #define VPP2_GCLK_CTRL1 0x1973 104 #define VPP2_SC_GCLK_CTRL 0x1974 105 #define VPP2_MISC1 0x1976 106 #define VPP2_DNLP_CTRL_00 0x1981 107 #define VPP2_DNLP_CTRL_01 0x1982 108 #define VPP2_DNLP_CTRL_02 0x1983 109 #define VPP2_DNLP_CTRL_03 0x1984 110 #define VPP2_DNLP_CTRL_04 0x1985 111 #define VPP2_DNLP_CTRL_05 0x1986 112 #define VPP2_DNLP_CTRL_06 0x1987 113 #define VPP2_DNLP_CTRL_07 0x1988 114 #define VPP2_DNLP_CTRL_08 0x1989 115 #define VPP2_DNLP_CTRL_09 0x198a 116 #define VPP2_DNLP_CTRL_10 0x198b 117 #define VPP2_DNLP_CTRL_11 0x198c 118 #define VPP2_DNLP_CTRL_12 0x198d 119 #define VPP2_DNLP_CTRL_13 0x198e 120 #define VPP2_DNLP_CTRL_14 0x198f 121 #define VPP2_DNLP_CTRL_15 0x1990 122 #define VPP2_VE_ENABLE_CTRL 0x19a1 123 #define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 124 #define VPP2_VE_DEMO_CENTER_BAR 0x19a3 125 #define VPP2_VE_H_V_SIZE 0x19a4 126 #define VPP2_VDO_MEAS_CTRL 0x19a8 127 #define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9 128 #define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa 129 #define VPP2_OSD_VSC_PHASE_STEP 0x19c0 130 #define VPP2_OSD_VSC_INI_PHASE 0x19c1 131 #define VPP2_OSD_VSC_CTRL0 0x19c2 132 #define VPP2_OSD_HSC_PHASE_STEP 0x19c3 133 #define VPP2_OSD_HSC_INI_PHASE 0x19c4 134 #define VPP2_OSD_HSC_CTRL0 0x19c5 135 #define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6 136 #define VPP2_OSD_SC_DUMMY_DATA 0x19c7 137 #define VPP2_OSD_SC_CTRL0 0x19c8 138 #define VPP2_OSD_SCI_WH_M1 0x19c9 139 #define VPP2_OSD_SCO_H_START_END 0x19ca 140 #define VPP2_OSD_SCO_V_START_END 0x19cb 141 #define VPP2_OSD_SCALE_COEF_IDX 0x19cc 142 #define VPP2_OSD_SCALE_COEF 0x19cd 143 #define VPP2_INT_LINE_NUM 0x19ce 144 145 /* viu */ 146 #define VIU_ADDR_START 0x1a00 147 #define VIU_ADDR_END 0x1aff 148 #define VIU_SW_RESET 0x1a01 149 #define VIU_MISC_CTRL0 0x1a06 150 #define VIU_MISC_CTRL1 0x1a07 151 #define D2D3_INTF_LENGTH 0x1a08 152 #define D2D3_INTF_CTRL0 0x1a09 153 #define VIU_OSD1_CTRL_STAT 0x1a10 154 #define VIU_OSD1_CTRL_STAT2 0x1a2d 155 #define VIU_OSD1_COLOR_ADDR 0x1a11 156 #define VIU_OSD1_COLOR 0x1a12 157 #define VIU_OSD1_TCOLOR_AG0 0x1a17 158 #define VIU_OSD1_TCOLOR_AG1 0x1a18 159 #define VIU_OSD1_TCOLOR_AG2 0x1a19 160 #define VIU_OSD1_TCOLOR_AG3 0x1a1a 161 #define VIU_OSD1_BLK0_CFG_W0 0x1a1b 162 #define VIU_OSD1_BLK1_CFG_W0 0x1a1f 163 #define VIU_OSD1_BLK2_CFG_W0 0x1a23 164 #define VIU_OSD1_BLK3_CFG_W0 0x1a27 165 #define VIU_OSD1_BLK0_CFG_W1 0x1a1c 166 #define VIU_OSD1_BLK1_CFG_W1 0x1a20 167 #define VIU_OSD1_BLK2_CFG_W1 0x1a24 168 #define VIU_OSD1_BLK3_CFG_W1 0x1a28 169 #define VIU_OSD1_BLK0_CFG_W2 0x1a1d 170 #define VIU_OSD1_BLK1_CFG_W2 0x1a21 171 #define VIU_OSD1_BLK2_CFG_W2 0x1a25 172 #define VIU_OSD1_BLK3_CFG_W2 0x1a29 173 #define VIU_OSD1_BLK0_CFG_W3 0x1a1e 174 #define VIU_OSD1_BLK1_CFG_W3 0x1a22 175 #define VIU_OSD1_BLK2_CFG_W3 0x1a26 176 #define VIU_OSD1_BLK3_CFG_W3 0x1a2a 177 #define VIU_OSD1_BLK0_CFG_W4 0x1a13 178 #define VIU_OSD1_BLK1_CFG_W4 0x1a14 179 #define VIU_OSD1_BLK2_CFG_W4 0x1a15 180 #define VIU_OSD1_BLK3_CFG_W4 0x1a16 181 #define VIU_OSD1_FIFO_CTRL_STAT 0x1a2b 182 #define VIU_OSD1_TEST_RDDATA 0x1a2c 183 #define VIU_OSD1_PROT_CTRL 0x1a2e 184 #define VIU_OSD2_CTRL_STAT 0x1a30 185 #define VIU_OSD2_CTRL_STAT2 0x1a4d 186 #define VIU_OSD2_COLOR_ADDR 0x1a31 187 #define VIU_OSD2_COLOR 0x1a32 188 #define VIU_OSD2_HL1_H_START_END 0x1a33 189 #define VIU_OSD2_HL1_V_START_END 0x1a34 190 #define VIU_OSD2_HL2_H_START_END 0x1a35 191 #define VIU_OSD2_HL2_V_START_END 0x1a36 192 #define VIU_OSD2_TCOLOR_AG0 0x1a37 193 #define VIU_OSD2_TCOLOR_AG1 0x1a38 194 #define VIU_OSD2_TCOLOR_AG2 0x1a39 195 #define VIU_OSD2_TCOLOR_AG3 0x1a3a 196 #define VIU_OSD2_BLK0_CFG_W0 0x1a3b 197 #define VIU_OSD2_BLK1_CFG_W0 0x1a3f 198 #define VIU_OSD2_BLK2_CFG_W0 0x1a43 199 #define VIU_OSD2_BLK3_CFG_W0 0x1a47 200 #define VIU_OSD2_BLK0_CFG_W1 0x1a3c 201 #define VIU_OSD2_BLK1_CFG_W1 0x1a40 202 #define VIU_OSD2_BLK2_CFG_W1 0x1a44 203 #define VIU_OSD2_BLK3_CFG_W1 0x1a48 204 #define VIU_OSD2_BLK0_CFG_W2 0x1a3d 205 #define VIU_OSD2_BLK1_CFG_W2 0x1a41 206 #define VIU_OSD2_BLK2_CFG_W2 0x1a45 207 #define VIU_OSD2_BLK3_CFG_W2 0x1a49 208 #define VIU_OSD2_BLK0_CFG_W3 0x1a3e 209 #define VIU_OSD2_BLK1_CFG_W3 0x1a42 210 #define VIU_OSD2_BLK2_CFG_W3 0x1a46 211 #define VIU_OSD2_BLK3_CFG_W3 0x1a4a 212 #define VIU_OSD2_BLK0_CFG_W4 0x1a64 213 #define VIU_OSD2_BLK1_CFG_W4 0x1a65 214 #define VIU_OSD2_BLK2_CFG_W4 0x1a66 215 #define VIU_OSD2_BLK3_CFG_W4 0x1a67 216 #define VIU_OSD2_FIFO_CTRL_STAT 0x1a4b 217 #define VIU_OSD2_TEST_RDDATA 0x1a4c 218 #define VIU_OSD2_PROT_CTRL 0x1a4e 219 220 #define VD1_IF0_GEN_REG 0x1a50 221 #define VD1_IF0_CANVAS0 0x1a51 222 #define VD1_IF0_CANVAS1 0x1a52 223 #define VD1_IF0_LUMA_X0 0x1a53 224 #define VD1_IF0_LUMA_Y0 0x1a54 225 #define VD1_IF0_CHROMA_X0 0x1a55 226 #define VD1_IF0_CHROMA_Y0 0x1a56 227 #define VD1_IF0_LUMA_X1 0x1a57 228 #define VD1_IF0_LUMA_Y1 0x1a58 229 #define VD1_IF0_CHROMA_X1 0x1a59 230 #define VD1_IF0_CHROMA_Y1 0x1a5a 231 #define VD1_IF0_RPT_LOOP 0x1a5b 232 #define VD1_IF0_LUMA0_RPT_PAT 0x1a5c 233 #define VD1_IF0_CHROMA0_RPT_PAT 0x1a5d 234 #define VD1_IF0_LUMA1_RPT_PAT 0x1a5e 235 #define VD1_IF0_CHROMA1_RPT_PAT 0x1a5f 236 #define VD1_IF0_LUMA_PSEL 0x1a60 237 #define VD1_IF0_CHROMA_PSEL 0x1a61 238 #define VD1_IF0_DUMMY_PIXEL 0x1a62 239 #define VD1_IF0_LUMA_FIFO_SIZE 0x1a63 240 #define VD1_IF0_RANGE_MAP_Y 0x1a6a 241 #define VD1_IF0_RANGE_MAP_CB 0x1a6b 242 #define VD1_IF0_RANGE_MAP_CR 0x1a6c 243 #define VD1_IF0_GEN_REG2 0x1a6d 244 #define VD1_IF0_PROT_CNTL 0x1a6e 245 #define VIU_VD1_FMT_CTRL 0x1a68 246 #define VIU_VD1_FMT_W 0x1a69 247 #define VD2_IF0_GEN_REG 0x1a70 248 #define VD2_IF0_CANVAS0 0x1a71 249 #define VD2_IF0_CANVAS1 0x1a72 250 #define VD2_IF0_LUMA_X0 0x1a73 251 #define VD2_IF0_LUMA_Y0 0x1a74 252 #define VD2_IF0_CHROMA_X0 0x1a75 253 #define VD2_IF0_CHROMA_Y0 0x1a76 254 #define VD2_IF0_LUMA_X1 0x1a77 255 #define VD2_IF0_LUMA_Y1 0x1a78 256 #define VD2_IF0_CHROMA_X1 0x1a79 257 #define VD2_IF0_CHROMA_Y1 0x1a7a 258 #define VD2_IF0_RPT_LOOP 0x1a7b 259 #define VD2_IF0_LUMA0_RPT_PAT 0x1a7c 260 #define VD2_IF0_CHROMA0_RPT_PAT 0x1a7d 261 #define VD2_IF0_LUMA1_RPT_PAT 0x1a7e 262 #define VD2_IF0_CHROMA1_RPT_PAT 0x1a7f 263 #define VD2_IF0_LUMA_PSEL 0x1a80 264 #define VD2_IF0_CHROMA_PSEL 0x1a81 265 #define VD2_IF0_DUMMY_PIXEL 0x1a82 266 #define VD2_IF0_LUMA_FIFO_SIZE 0x1a83 267 #define VD2_IF0_RANGE_MAP_Y 0x1a8a 268 #define VD2_IF0_RANGE_MAP_CB 0x1a8b 269 #define VD2_IF0_RANGE_MAP_CR 0x1a8c 270 #define VD2_IF0_GEN_REG2 0x1a8d 271 #define VD2_IF0_PROT_CNTL 0x1a8e 272 #define VIU_VD2_FMT_CTRL 0x1a88 273 #define VIU_VD2_FMT_W 0x1a89 274 275 /* VIU Matrix Registers */ 276 #define VIU_OSD1_MATRIX_CTRL 0x1a90 277 #define VIU_OSD1_MATRIX_COEF00_01 0x1a91 278 #define VIU_OSD1_MATRIX_COEF02_10 0x1a92 279 #define VIU_OSD1_MATRIX_COEF11_12 0x1a93 280 #define VIU_OSD1_MATRIX_COEF20_21 0x1a94 281 #define VIU_OSD1_MATRIX_COLMOD_COEF42 0x1a95 282 #define VIU_OSD1_MATRIX_OFFSET0_1 0x1a96 283 #define VIU_OSD1_MATRIX_OFFSET2 0x1a97 284 #define VIU_OSD1_MATRIX_PRE_OFFSET0_1 0x1a98 285 #define VIU_OSD1_MATRIX_PRE_OFFSET2 0x1a99 286 #define VIU_OSD1_MATRIX_COEF22_30 0x1a9d 287 #define VIU_OSD1_MATRIX_COEF31_32 0x1a9e 288 #define VIU_OSD1_MATRIX_COEF40_41 0x1a9f 289 #define VIU_OSD1_EOTF_CTL 0x1ad4 290 #define VIU_OSD1_EOTF_COEF00_01 0x1ad5 291 #define VIU_OSD1_EOTF_COEF02_10 0x1ad6 292 #define VIU_OSD1_EOTF_COEF11_12 0x1ad7 293 #define VIU_OSD1_EOTF_COEF20_21 0x1ad8 294 #define VIU_OSD1_EOTF_COEF22_RS 0x1ad9 295 #define VIU_OSD1_EOTF_LUT_ADDR_PORT 0x1ada 296 #define VIU_OSD1_EOTF_LUT_DATA_PORT 0x1adb 297 #define VIU_OSD1_OETF_CTL 0x1adc 298 #define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add 299 #define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade 300 301 /* vpp */ 302 #define VPP_DUMMY_DATA 0x1d00 303 #define VPP_LINE_IN_LENGTH 0x1d01 304 #define VPP_PIC_IN_HEIGHT 0x1d02 305 #define VPP_SCALE_COEF_IDX 0x1d03 306 #define VPP_SCALE_COEF 0x1d04 307 #define VPP_VSC_REGION12_STARTP 0x1d05 308 #define VPP_VSC_REGION34_STARTP 0x1d06 309 #define VPP_VSC_REGION4_ENDP 0x1d07 310 #define VPP_VSC_START_PHASE_STEP 0x1d08 311 #define VPP_VSC_REGION0_PHASE_SLOPE 0x1d09 312 #define VPP_VSC_REGION1_PHASE_SLOPE 0x1d0a 313 #define VPP_VSC_REGION3_PHASE_SLOPE 0x1d0b 314 #define VPP_VSC_REGION4_PHASE_SLOPE 0x1d0c 315 #define VPP_VSC_PHASE_CTRL 0x1d0d 316 #define VPP_VSC_INI_PHASE 0x1d0e 317 #define VPP_HSC_REGION12_STARTP 0x1d10 318 #define VPP_HSC_REGION34_STARTP 0x1d11 319 #define VPP_HSC_REGION4_ENDP 0x1d12 320 #define VPP_HSC_START_PHASE_STEP 0x1d13 321 #define VPP_HSC_REGION0_PHASE_SLOPE 0x1d14 322 #define VPP_HSC_REGION1_PHASE_SLOPE 0x1d15 323 #define VPP_HSC_REGION3_PHASE_SLOPE 0x1d16 324 #define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17 325 #define VPP_HSC_PHASE_CTRL 0x1d18 326 #define VPP_SC_MISC 0x1d19 327 #define VPP_PREBLEND_VD1_H_START_END 0x1d1a 328 #define VPP_PREBLEND_VD1_V_START_END 0x1d1b 329 #define VPP_POSTBLEND_VD1_H_START_END 0x1d1c 330 #define VPP_POSTBLEND_VD1_V_START_END 0x1d1d 331 #define VPP_BLEND_VD2_H_START_END 0x1d1e 332 #define VPP_BLEND_VD2_V_START_END 0x1d1f 333 #define VPP_PREBLEND_H_SIZE 0x1d20 334 #define VPP_POSTBLEND_H_SIZE 0x1d21 335 #define VPP_HOLD_LINES 0x1d22 336 #define VPP_BLEND_ONECOLOR_CTRL 0x1d23 337 #define VPP_PREBLEND_CURRENT_XY 0x1d24 338 #define VPP_POSTBLEND_CURRENT_XY 0x1d25 339 #define VPP_MISC 0x1d26 340 #define VPP_PREBLEND_ENABLE BIT(6) 341 #define VPP_POSTBLEND_ENABLE BIT(7) 342 #define VPP_OSD2_ALPHA_PREMULT BIT(8) 343 #define VPP_OSD1_ALPHA_PREMULT BIT(9) 344 #define VPP_VD1_POSTBLEND BIT(10) 345 #define VPP_VD2_POSTBLEND BIT(11) 346 #define VPP_OSD1_POSTBLEND BIT(12) 347 #define VPP_OSD2_POSTBLEND BIT(13) 348 #define VPP_VD1_PREBLEND BIT(14) 349 #define VPP_VD2_PREBLEND BIT(15) 350 #define VPP_OSD1_PREBLEND BIT(16) 351 #define VPP_OSD2_PREBLEND BIT(17) 352 #define VPP_OFIFO_SIZE 0x1d27 353 #define VPP_FIFO_STATUS 0x1d28 354 #define VPP_SMOKE_CTRL 0x1d29 355 #define VPP_SMOKE1_VAL 0x1d2a 356 #define VPP_SMOKE2_VAL 0x1d2b 357 #define VPP_SMOKE3_VAL 0x1d2c 358 #define VPP_SMOKE1_H_START_END 0x1d2d 359 #define VPP_SMOKE1_V_START_END 0x1d2e 360 #define VPP_SMOKE2_H_START_END 0x1d2f 361 #define VPP_SMOKE2_V_START_END 0x1d30 362 #define VPP_SMOKE3_H_START_END 0x1d31 363 #define VPP_SMOKE3_V_START_END 0x1d32 364 #define VPP_SCO_FIFO_CTRL 0x1d33 365 #define VPP_HSC_PHASE_CTRL1 0x1d34 366 #define VPP_HSC_INI_PAT_CTRL 0x1d35 367 #define VPP_VADJ_CTRL 0x1d40 368 #define VPP_VADJ1_Y 0x1d41 369 #define VPP_VADJ1_MA_MB 0x1d42 370 #define VPP_VADJ1_MC_MD 0x1d43 371 #define VPP_VADJ2_Y 0x1d44 372 #define VPP_VADJ2_MA_MB 0x1d45 373 #define VPP_VADJ2_MC_MD 0x1d46 374 #define VPP_HSHARP_CTRL 0x1d50 375 #define VPP_HSHARP_LUMA_THRESH01 0x1d51 376 #define VPP_HSHARP_LUMA_THRESH23 0x1d52 377 #define VPP_HSHARP_CHROMA_THRESH01 0x1d53 378 #define VPP_HSHARP_CHROMA_THRESH23 0x1d54 379 #define VPP_HSHARP_LUMA_GAIN 0x1d55 380 #define VPP_HSHARP_CHROMA_GAIN 0x1d56 381 #define VPP_MATRIX_PROBE_COLOR 0x1d5c 382 #define VPP_MATRIX_HL_COLOR 0x1d5d 383 #define VPP_MATRIX_PROBE_POS 0x1d5e 384 #define VPP_MATRIX_CTRL 0x1d5f 385 #define VPP_MATRIX_COEF00_01 0x1d60 386 #define VPP_MATRIX_COEF02_10 0x1d61 387 #define VPP_MATRIX_COEF11_12 0x1d62 388 #define VPP_MATRIX_COEF20_21 0x1d63 389 #define VPP_MATRIX_COEF22 0x1d64 390 #define VPP_MATRIX_OFFSET0_1 0x1d65 391 #define VPP_MATRIX_OFFSET2 0x1d66 392 #define VPP_MATRIX_PRE_OFFSET0_1 0x1d67 393 #define VPP_MATRIX_PRE_OFFSET2 0x1d68 394 #define VPP_DUMMY_DATA1 0x1d69 395 #define VPP_GAINOFF_CTRL0 0x1d6a 396 #define VPP_GAINOFF_CTRL1 0x1d6b 397 #define VPP_GAINOFF_CTRL2 0x1d6c 398 #define VPP_GAINOFF_CTRL3 0x1d6d 399 #define VPP_GAINOFF_CTRL4 0x1d6e 400 #define VPP_CHROMA_ADDR_PORT 0x1d70 401 #define VPP_CHROMA_DATA_PORT 0x1d71 402 #define VPP_GCLK_CTRL0 0x1d72 403 #define VPP_GCLK_CTRL1 0x1d73 404 #define VPP_SC_GCLK_CTRL 0x1d74 405 #define VPP_MISC1 0x1d76 406 #define VPP_BLACKEXT_CTRL 0x1d80 407 #define VPP_DNLP_CTRL_00 0x1d81 408 #define VPP_DNLP_CTRL_01 0x1d82 409 #define VPP_DNLP_CTRL_02 0x1d83 410 #define VPP_DNLP_CTRL_03 0x1d84 411 #define VPP_DNLP_CTRL_04 0x1d85 412 #define VPP_DNLP_CTRL_05 0x1d86 413 #define VPP_DNLP_CTRL_06 0x1d87 414 #define VPP_DNLP_CTRL_07 0x1d88 415 #define VPP_DNLP_CTRL_08 0x1d89 416 #define VPP_DNLP_CTRL_09 0x1d8a 417 #define VPP_DNLP_CTRL_10 0x1d8b 418 #define VPP_DNLP_CTRL_11 0x1d8c 419 #define VPP_DNLP_CTRL_12 0x1d8d 420 #define VPP_DNLP_CTRL_13 0x1d8e 421 #define VPP_DNLP_CTRL_14 0x1d8f 422 #define VPP_DNLP_CTRL_15 0x1d90 423 #define VPP_PEAKING_HGAIN 0x1d91 424 #define VPP_PEAKING_VGAIN 0x1d92 425 #define VPP_PEAKING_NLP_1 0x1d93 426 #define VPP_DOLBY_CTRL 0x1d93 427 #define VPP_PEAKING_NLP_2 0x1d94 428 #define VPP_PEAKING_NLP_3 0x1d95 429 #define VPP_PEAKING_NLP_4 0x1d96 430 #define VPP_PEAKING_NLP_5 0x1d97 431 #define VPP_SHARP_LIMIT 0x1d98 432 #define VPP_VLTI_CTRL 0x1d99 433 #define VPP_HLTI_CTRL 0x1d9a 434 #define VPP_CTI_CTRL 0x1d9b 435 #define VPP_BLUE_STRETCH_1 0x1d9c 436 #define VPP_BLUE_STRETCH_2 0x1d9d 437 #define VPP_BLUE_STRETCH_3 0x1d9e 438 #define VPP_CCORING_CTRL 0x1da0 439 #define VPP_VE_ENABLE_CTRL 0x1da1 440 #define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2 441 #define VPP_VE_DEMO_CENTER_BAR 0x1da3 442 #define VPP_VE_H_V_SIZE 0x1da4 443 #define VPP_VDO_MEAS_CTRL 0x1da8 444 #define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9 445 #define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa 446 #define VPP_INPUT_CTRL 0x1dab 447 #define VPP_CTI_CTRL2 0x1dac 448 #define VPP_PEAKING_SAT_THD1 0x1dad 449 #define VPP_PEAKING_SAT_THD2 0x1dae 450 #define VPP_PEAKING_SAT_THD3 0x1daf 451 #define VPP_PEAKING_SAT_THD4 0x1db0 452 #define VPP_PEAKING_SAT_THD5 0x1db1 453 #define VPP_PEAKING_SAT_THD6 0x1db2 454 #define VPP_PEAKING_SAT_THD7 0x1db3 455 #define VPP_PEAKING_SAT_THD8 0x1db4 456 #define VPP_PEAKING_SAT_THD9 0x1db5 457 #define VPP_PEAKING_GAIN_ADD1 0x1db6 458 #define VPP_PEAKING_GAIN_ADD2 0x1db7 459 #define VPP_PEAKING_DNLP 0x1db8 460 #define VPP_SHARP_DEMO_WIN_CTRL1 0x1db9 461 #define VPP_SHARP_DEMO_WIN_CTRL2 0x1dba 462 #define VPP_FRONT_HLTI_CTRL 0x1dbb 463 #define VPP_FRONT_CTI_CTRL 0x1dbc 464 #define VPP_FRONT_CTI_CTRL2 0x1dbd 465 #define VPP_OSD_VSC_PHASE_STEP 0x1dc0 466 #define VPP_OSD_VSC_INI_PHASE 0x1dc1 467 #define VPP_OSD_VSC_CTRL0 0x1dc2 468 #define VPP_OSD_HSC_PHASE_STEP 0x1dc3 469 #define VPP_OSD_HSC_INI_PHASE 0x1dc4 470 #define VPP_OSD_HSC_CTRL0 0x1dc5 471 #define VPP_OSD_HSC_INI_PAT_CTRL 0x1dc6 472 #define VPP_OSD_SC_DUMMY_DATA 0x1dc7 473 #define VPP_OSD_SC_CTRL0 0x1dc8 474 #define VPP_OSD_SCI_WH_M1 0x1dc9 475 #define VPP_OSD_SCO_H_START_END 0x1dca 476 #define VPP_OSD_SCO_V_START_END 0x1dcb 477 #define VPP_OSD_SCALE_COEF_IDX 0x1dcc 478 #define VPP_OSD_SCALE_COEF 0x1dcd 479 #define VPP_INT_LINE_NUM 0x1dce 480 481 /* viu2 */ 482 #define VIU2_ADDR_START 0x1e00 483 #define VIU2_ADDR_END 0x1eff 484 #define VIU2_SW_RESET 0x1e01 485 #define VIU2_OSD1_CTRL_STAT 0x1e10 486 #define VIU2_OSD1_CTRL_STAT2 0x1e2d 487 #define VIU2_OSD1_COLOR_ADDR 0x1e11 488 #define VIU2_OSD1_COLOR 0x1e12 489 #define VIU2_OSD1_TCOLOR_AG0 0x1e17 490 #define VIU2_OSD1_TCOLOR_AG1 0x1e18 491 #define VIU2_OSD1_TCOLOR_AG2 0x1e19 492 #define VIU2_OSD1_TCOLOR_AG3 0x1e1a 493 #define VIU2_OSD1_BLK0_CFG_W0 0x1e1b 494 #define VIU2_OSD1_BLK1_CFG_W0 0x1e1f 495 #define VIU2_OSD1_BLK2_CFG_W0 0x1e23 496 #define VIU2_OSD1_BLK3_CFG_W0 0x1e27 497 #define VIU2_OSD1_BLK0_CFG_W1 0x1e1c 498 #define VIU2_OSD1_BLK1_CFG_W1 0x1e20 499 #define VIU2_OSD1_BLK2_CFG_W1 0x1e24 500 #define VIU2_OSD1_BLK3_CFG_W1 0x1e28 501 #define VIU2_OSD1_BLK0_CFG_W2 0x1e1d 502 #define VIU2_OSD1_BLK1_CFG_W2 0x1e21 503 #define VIU2_OSD1_BLK2_CFG_W2 0x1e25 504 #define VIU2_OSD1_BLK3_CFG_W2 0x1e29 505 #define VIU2_OSD1_BLK0_CFG_W3 0x1e1e 506 #define VIU2_OSD1_BLK1_CFG_W3 0x1e22 507 #define VIU2_OSD1_BLK2_CFG_W3 0x1e26 508 #define VIU2_OSD1_BLK3_CFG_W3 0x1e2a 509 #define VIU2_OSD1_BLK0_CFG_W4 0x1e13 510 #define VIU2_OSD1_BLK1_CFG_W4 0x1e14 511 #define VIU2_OSD1_BLK2_CFG_W4 0x1e15 512 #define VIU2_OSD1_BLK3_CFG_W4 0x1e16 513 #define VIU2_OSD1_FIFO_CTRL_STAT 0x1e2b 514 #define VIU2_OSD1_TEST_RDDATA 0x1e2c 515 #define VIU2_OSD1_PROT_CTRL 0x1e2e 516 #define VIU2_OSD2_CTRL_STAT 0x1e30 517 #define VIU2_OSD2_CTRL_STAT2 0x1e4d 518 #define VIU2_OSD2_COLOR_ADDR 0x1e31 519 #define VIU2_OSD2_COLOR 0x1e32 520 #define VIU2_OSD2_HL1_H_START_END 0x1e33 521 #define VIU2_OSD2_HL1_V_START_END 0x1e34 522 #define VIU2_OSD2_HL2_H_START_END 0x1e35 523 #define VIU2_OSD2_HL2_V_START_END 0x1e36 524 #define VIU2_OSD2_TCOLOR_AG0 0x1e37 525 #define VIU2_OSD2_TCOLOR_AG1 0x1e38 526 #define VIU2_OSD2_TCOLOR_AG2 0x1e39 527 #define VIU2_OSD2_TCOLOR_AG3 0x1e3a 528 #define VIU2_OSD2_BLK0_CFG_W0 0x1e3b 529 #define VIU2_OSD2_BLK1_CFG_W0 0x1e3f 530 #define VIU2_OSD2_BLK2_CFG_W0 0x1e43 531 #define VIU2_OSD2_BLK3_CFG_W0 0x1e47 532 #define VIU2_OSD2_BLK0_CFG_W1 0x1e3c 533 #define VIU2_OSD2_BLK1_CFG_W1 0x1e40 534 #define VIU2_OSD2_BLK2_CFG_W1 0x1e44 535 #define VIU2_OSD2_BLK3_CFG_W1 0x1e48 536 #define VIU2_OSD2_BLK0_CFG_W2 0x1e3d 537 #define VIU2_OSD2_BLK1_CFG_W2 0x1e41 538 #define VIU2_OSD2_BLK2_CFG_W2 0x1e45 539 #define VIU2_OSD2_BLK3_CFG_W2 0x1e49 540 #define VIU2_OSD2_BLK0_CFG_W3 0x1e3e 541 #define VIU2_OSD2_BLK1_CFG_W3 0x1e42 542 #define VIU2_OSD2_BLK2_CFG_W3 0x1e46 543 #define VIU2_OSD2_BLK3_CFG_W3 0x1e4a 544 #define VIU2_OSD2_BLK0_CFG_W4 0x1e64 545 #define VIU2_OSD2_BLK1_CFG_W4 0x1e65 546 #define VIU2_OSD2_BLK2_CFG_W4 0x1e66 547 #define VIU2_OSD2_BLK3_CFG_W4 0x1e67 548 #define VIU2_OSD2_FIFO_CTRL_STAT 0x1e4b 549 #define VIU2_OSD2_TEST_RDDATA 0x1e4c 550 #define VIU2_OSD2_PROT_CTRL 0x1e4e 551 #define VIU2_VD1_IF0_GEN_REG 0x1e50 552 #define VIU2_VD1_IF0_CANVAS0 0x1e51 553 #define VIU2_VD1_IF0_CANVAS1 0x1e52 554 #define VIU2_VD1_IF0_LUMA_X0 0x1e53 555 #define VIU2_VD1_IF0_LUMA_Y0 0x1e54 556 #define VIU2_VD1_IF0_CHROMA_X0 0x1e55 557 #define VIU2_VD1_IF0_CHROMA_Y0 0x1e56 558 #define VIU2_VD1_IF0_LUMA_X1 0x1e57 559 #define VIU2_VD1_IF0_LUMA_Y1 0x1e58 560 #define VIU2_VD1_IF0_CHROMA_X1 0x1e59 561 #define VIU2_VD1_IF0_CHROMA_Y1 0x1e5a 562 #define VIU2_VD1_IF0_RPT_LOOP 0x1e5b 563 #define VIU2_VD1_IF0_LUMA0_RPT_PAT 0x1e5c 564 #define VIU2_VD1_IF0_CHROMA0_RPT_PAT 0x1e5d 565 #define VIU2_VD1_IF0_LUMA1_RPT_PAT 0x1e5e 566 #define VIU2_VD1_IF0_CHROMA1_RPT_PAT 0x1e5f 567 #define VIU2_VD1_IF0_LUMA_PSEL 0x1e60 568 #define VIU2_VD1_IF0_CHROMA_PSEL 0x1e61 569 #define VIU2_VD1_IF0_DUMMY_PIXEL 0x1e62 570 #define VIU2_VD1_IF0_LUMA_FIFO_SIZE 0x1e63 571 #define VIU2_VD1_IF0_RANGE_MAP_Y 0x1e6a 572 #define VIU2_VD1_IF0_RANGE_MAP_CB 0x1e6b 573 #define VIU2_VD1_IF0_RANGE_MAP_CR 0x1e6c 574 #define VIU2_VD1_IF0_GEN_REG2 0x1e6d 575 #define VIU2_VD1_IF0_PROT_CNTL 0x1e6e 576 #define VIU2_VD1_FMT_CTRL 0x1e68 577 #define VIU2_VD1_FMT_W 0x1e69 578 579 /* encode */ 580 #define ENCP_VFIFO2VD_CTL 0x1b58 581 #define ENCP_VFIFO2VD_PIXEL_START 0x1b59 582 #define ENCP_VFIFO2VD_PIXEL_END 0x1b5a 583 #define ENCP_VFIFO2VD_LINE_TOP_START 0x1b5b 584 #define ENCP_VFIFO2VD_LINE_TOP_END 0x1b5c 585 #define ENCP_VFIFO2VD_LINE_BOT_START 0x1b5d 586 #define ENCP_VFIFO2VD_LINE_BOT_END 0x1b5e 587 #define VENC_SYNC_ROUTE 0x1b60 588 #define VENC_VIDEO_EXSRC 0x1b61 589 #define VENC_DVI_SETTING 0x1b62 590 #define VENC_C656_CTRL 0x1b63 591 #define VENC_UPSAMPLE_CTRL0 0x1b64 592 #define VENC_UPSAMPLE_CTRL1 0x1b65 593 #define VENC_UPSAMPLE_CTRL2 0x1b66 594 #define TCON_INVERT_CTL 0x1b67 595 #define VENC_VIDEO_PROG_MODE 0x1b68 596 #define VENC_ENCI_LINE 0x1b69 597 #define VENC_ENCI_PIXEL 0x1b6a 598 #define VENC_ENCP_LINE 0x1b6b 599 #define VENC_ENCP_PIXEL 0x1b6c 600 #define VENC_STATA 0x1b6d 601 #define VENC_INTCTRL 0x1b6e 602 #define VENC_INTFLAG 0x1b6f 603 #define VENC_VIDEO_TST_EN 0x1b70 604 #define VENC_VIDEO_TST_MDSEL 0x1b71 605 #define VENC_VIDEO_TST_Y 0x1b72 606 #define VENC_VIDEO_TST_CB 0x1b73 607 #define VENC_VIDEO_TST_CR 0x1b74 608 #define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75 609 #define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76 610 #define VENC_VIDEO_TST_VDCNT_STSET 0x1b77 611 #define VENC_VDAC_DACSEL0 0x1b78 612 #define VENC_VDAC_DACSEL1 0x1b79 613 #define VENC_VDAC_DACSEL2 0x1b7a 614 #define VENC_VDAC_DACSEL3 0x1b7b 615 #define VENC_VDAC_DACSEL4 0x1b7c 616 #define VENC_VDAC_DACSEL5 0x1b7d 617 #define VENC_VDAC_SETTING 0x1b7e 618 #define VENC_VDAC_TST_VAL 0x1b7f 619 #define VENC_VDAC_DAC0_GAINCTRL 0x1bf0 620 #define VENC_VDAC_DAC0_OFFSET 0x1bf1 621 #define VENC_VDAC_DAC1_GAINCTRL 0x1bf2 622 #define VENC_VDAC_DAC1_OFFSET 0x1bf3 623 #define VENC_VDAC_DAC2_GAINCTRL 0x1bf4 624 #define VENC_VDAC_DAC2_OFFSET 0x1bf5 625 #define VENC_VDAC_DAC3_GAINCTRL 0x1bf6 626 #define VENC_VDAC_DAC3_OFFSET 0x1bf7 627 #define VENC_VDAC_DAC4_GAINCTRL 0x1bf8 628 #define VENC_VDAC_DAC4_OFFSET 0x1bf9 629 #define VENC_VDAC_DAC5_GAINCTRL 0x1bfa 630 #define VENC_VDAC_DAC5_OFFSET 0x1bfb 631 #define VENC_VDAC_FIFO_CTRL 0x1bfc 632 #define ENCL_TCON_INVERT_CTL 0x1bfd 633 #define ENCP_VIDEO_EN 0x1b80 634 #define ENCP_VIDEO_SYNC_MODE 0x1b81 635 #define ENCP_MACV_EN 0x1b82 636 #define ENCP_VIDEO_Y_SCL 0x1b83 637 #define ENCP_VIDEO_PB_SCL 0x1b84 638 #define ENCP_VIDEO_PR_SCL 0x1b85 639 #define ENCP_VIDEO_SYNC_SCL 0x1b86 640 #define ENCP_VIDEO_MACV_SCL 0x1b87 641 #define ENCP_VIDEO_Y_OFFST 0x1b88 642 #define ENCP_VIDEO_PB_OFFST 0x1b89 643 #define ENCP_VIDEO_PR_OFFST 0x1b8a 644 #define ENCP_VIDEO_SYNC_OFFST 0x1b8b 645 #define ENCP_VIDEO_MACV_OFFST 0x1b8c 646 #define ENCP_VIDEO_MODE 0x1b8d 647 #define ENCP_VIDEO_MODE_ADV 0x1b8e 648 #define ENCP_DBG_PX_RST 0x1b90 649 #define ENCP_DBG_LN_RST 0x1b91 650 #define ENCP_DBG_PX_INT 0x1b92 651 #define ENCP_DBG_LN_INT 0x1b93 652 #define ENCP_VIDEO_YFP1_HTIME 0x1b94 653 #define ENCP_VIDEO_YFP2_HTIME 0x1b95 654 #define ENCP_VIDEO_YC_DLY 0x1b96 655 #define ENCP_VIDEO_MAX_PXCNT 0x1b97 656 #define ENCP_VIDEO_HSPULS_BEGIN 0x1b98 657 #define ENCP_VIDEO_HSPULS_END 0x1b99 658 #define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a 659 #define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b 660 #define ENCP_VIDEO_VSPULS_END 0x1b9c 661 #define ENCP_VIDEO_VSPULS_BLINE 0x1b9d 662 #define ENCP_VIDEO_VSPULS_ELINE 0x1b9e 663 #define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f 664 #define ENCP_VIDEO_EQPULS_END 0x1ba0 665 #define ENCP_VIDEO_EQPULS_BLINE 0x1ba1 666 #define ENCP_VIDEO_EQPULS_ELINE 0x1ba2 667 #define ENCP_VIDEO_HAVON_END 0x1ba3 668 #define ENCP_VIDEO_HAVON_BEGIN 0x1ba4 669 #define ENCP_VIDEO_VAVON_ELINE 0x1baf 670 #define ENCP_VIDEO_VAVON_BLINE 0x1ba6 671 #define ENCP_VIDEO_HSO_BEGIN 0x1ba7 672 #define ENCP_VIDEO_HSO_END 0x1ba8 673 #define ENCP_VIDEO_VSO_BEGIN 0x1ba9 674 #define ENCP_VIDEO_VSO_END 0x1baa 675 #define ENCP_VIDEO_VSO_BLINE 0x1bab 676 #define ENCP_VIDEO_VSO_ELINE 0x1bac 677 #define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad 678 #define ENCP_VIDEO_MAX_LNCNT 0x1bae 679 #define ENCP_VIDEO_SY_VAL 0x1bb0 680 #define ENCP_VIDEO_SY2_VAL 0x1bb1 681 #define ENCP_VIDEO_BLANKY_VAL 0x1bb2 682 #define ENCP_VIDEO_BLANKPB_VAL 0x1bb3 683 #define ENCP_VIDEO_BLANKPR_VAL 0x1bb4 684 #define ENCP_VIDEO_HOFFST 0x1bb5 685 #define ENCP_VIDEO_VOFFST 0x1bb6 686 #define ENCP_VIDEO_RGB_CTRL 0x1bb7 687 #define ENCP_VIDEO_FILT_CTRL 0x1bb8 688 #define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9 689 #define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba 690 #define ENCP_VIDEO_MATRIX_CB 0x1bbb 691 #define ENCP_VIDEO_MATRIX_CR 0x1bbc 692 #define ENCP_VIDEO_RGBIN_CTRL 0x1bbd 693 #define ENCP_MACV_BLANKY_VAL 0x1bc0 694 #define ENCP_MACV_MAXY_VAL 0x1bc1 695 #define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2 696 #define ENCP_MACV_PSSYNC_STRT 0x1bc3 697 #define ENCP_MACV_AGC_STRT 0x1bc4 698 #define ENCP_MACV_AGC_END 0x1bc5 699 #define ENCP_MACV_WAVE_END 0x1bc6 700 #define ENCP_MACV_STRTLINE 0x1bc7 701 #define ENCP_MACV_ENDLINE 0x1bc8 702 #define ENCP_MACV_TS_CNT_MAX_L 0x1bc9 703 #define ENCP_MACV_TS_CNT_MAX_H 0x1bca 704 #define ENCP_MACV_TIME_DOWN 0x1bcb 705 #define ENCP_MACV_TIME_LO 0x1bcc 706 #define ENCP_MACV_TIME_UP 0x1bcd 707 #define ENCP_MACV_TIME_RST 0x1bce 708 #define ENCP_VBI_CTRL 0x1bd0 709 #define ENCP_VBI_SETTING 0x1bd1 710 #define ENCP_VBI_BEGIN 0x1bd2 711 #define ENCP_VBI_WIDTH 0x1bd3 712 #define ENCP_VBI_HVAL 0x1bd4 713 #define ENCP_VBI_DATA0 0x1bd5 714 #define ENCP_VBI_DATA1 0x1bd6 715 #define C656_HS_ST 0x1be0 716 #define C656_HS_ED 0x1be1 717 #define C656_VS_LNST_E 0x1be2 718 #define C656_VS_LNST_O 0x1be3 719 #define C656_VS_LNED_E 0x1be4 720 #define C656_VS_LNED_O 0x1be5 721 #define C656_FS_LNST 0x1be6 722 #define C656_FS_LNED 0x1be7 723 #define ENCI_VIDEO_MODE 0x1b00 724 #define ENCI_VIDEO_MODE_ADV 0x1b01 725 #define ENCI_VIDEO_FSC_ADJ 0x1b02 726 #define ENCI_VIDEO_BRIGHT 0x1b03 727 #define ENCI_VIDEO_CONT 0x1b04 728 #define ENCI_VIDEO_SAT 0x1b05 729 #define ENCI_VIDEO_HUE 0x1b06 730 #define ENCI_VIDEO_SCH 0x1b07 731 #define ENCI_SYNC_MODE 0x1b08 732 #define ENCI_SYNC_CTRL 0x1b09 733 #define ENCI_SYNC_HSO_BEGIN 0x1b0a 734 #define ENCI_SYNC_HSO_END 0x1b0b 735 #define ENCI_SYNC_VSO_EVN 0x1b0c 736 #define ENCI_SYNC_VSO_ODD 0x1b0d 737 #define ENCI_SYNC_VSO_EVNLN 0x1b0e 738 #define ENCI_SYNC_VSO_ODDLN 0x1b0f 739 #define ENCI_SYNC_HOFFST 0x1b10 740 #define ENCI_SYNC_VOFFST 0x1b11 741 #define ENCI_SYNC_ADJ 0x1b12 742 #define ENCI_RGB_SETTING 0x1b13 743 #define ENCI_DE_H_BEGIN 0x1b16 744 #define ENCI_DE_H_END 0x1b17 745 #define ENCI_DE_V_BEGIN_EVEN 0x1b18 746 #define ENCI_DE_V_END_EVEN 0x1b19 747 #define ENCI_DE_V_BEGIN_ODD 0x1b1a 748 #define ENCI_DE_V_END_ODD 0x1b1b 749 #define ENCI_VBI_SETTING 0x1b20 750 #define ENCI_VBI_CCDT_EVN 0x1b21 751 #define ENCI_VBI_CCDT_ODD 0x1b22 752 #define ENCI_VBI_CC525_LN 0x1b23 753 #define ENCI_VBI_CC625_LN 0x1b24 754 #define ENCI_VBI_WSSDT 0x1b25 755 #define ENCI_VBI_WSS_LN 0x1b26 756 #define ENCI_VBI_CGMSDT_L 0x1b27 757 #define ENCI_VBI_CGMSDT_H 0x1b28 758 #define ENCI_VBI_CGMS_LN 0x1b29 759 #define ENCI_VBI_TTX_HTIME 0x1b2a 760 #define ENCI_VBI_TTX_LN 0x1b2b 761 #define ENCI_VBI_TTXDT0 0x1b2c 762 #define ENCI_VBI_TTXDT1 0x1b2d 763 #define ENCI_VBI_TTXDT2 0x1b2e 764 #define ENCI_VBI_TTXDT3 0x1b2f 765 #define ENCI_MACV_N0 0x1b30 766 #define ENCI_MACV_N1 0x1b31 767 #define ENCI_MACV_N2 0x1b32 768 #define ENCI_MACV_N3 0x1b33 769 #define ENCI_MACV_N4 0x1b34 770 #define ENCI_MACV_N5 0x1b35 771 #define ENCI_MACV_N6 0x1b36 772 #define ENCI_MACV_N7 0x1b37 773 #define ENCI_MACV_N8 0x1b38 774 #define ENCI_MACV_N9 0x1b39 775 #define ENCI_MACV_N10 0x1b3a 776 #define ENCI_MACV_N11 0x1b3b 777 #define ENCI_MACV_N12 0x1b3c 778 #define ENCI_MACV_N13 0x1b3d 779 #define ENCI_MACV_N14 0x1b3e 780 #define ENCI_MACV_N15 0x1b3f 781 #define ENCI_MACV_N16 0x1b40 782 #define ENCI_MACV_N17 0x1b41 783 #define ENCI_MACV_N18 0x1b42 784 #define ENCI_MACV_N19 0x1b43 785 #define ENCI_MACV_N20 0x1b44 786 #define ENCI_MACV_N21 0x1b45 787 #define ENCI_MACV_N22 0x1b46 788 #define ENCI_DBG_PX_RST 0x1b48 789 #define ENCI_DBG_FLDLN_RST 0x1b49 790 #define ENCI_DBG_PX_INT 0x1b4a 791 #define ENCI_DBG_FLDLN_INT 0x1b4b 792 #define ENCI_DBG_MAXPX 0x1b4c 793 #define ENCI_DBG_MAXLN 0x1b4d 794 #define ENCI_MACV_MAX_AMP 0x1b50 795 #define ENCI_MACV_PULSE_LO 0x1b51 796 #define ENCI_MACV_PULSE_HI 0x1b52 797 #define ENCI_MACV_BKP_MAX 0x1b53 798 #define ENCI_CFILT_CTRL 0x1b54 799 #define ENCI_CFILT7 0x1b55 800 #define ENCI_YC_DELAY 0x1b56 801 #define ENCI_VIDEO_EN 0x1b57 802 #define ENCI_DVI_HSO_BEGIN 0x1c00 803 #define ENCI_DVI_HSO_END 0x1c01 804 #define ENCI_DVI_VSO_BLINE_EVN 0x1c02 805 #define ENCI_DVI_VSO_BLINE_ODD 0x1c03 806 #define ENCI_DVI_VSO_ELINE_EVN 0x1c04 807 #define ENCI_DVI_VSO_ELINE_ODD 0x1c05 808 #define ENCI_DVI_VSO_BEGIN_EVN 0x1c06 809 #define ENCI_DVI_VSO_BEGIN_ODD 0x1c07 810 #define ENCI_DVI_VSO_END_EVN 0x1c08 811 #define ENCI_DVI_VSO_END_ODD 0x1c09 812 #define ENCI_CFILT_CTRL2 0x1c0a 813 #define ENCI_DACSEL_0 0x1c0b 814 #define ENCI_DACSEL_1 0x1c0c 815 #define ENCP_DACSEL_0 0x1c0d 816 #define ENCP_DACSEL_1 0x1c0e 817 #define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f 818 #define ENCI_TST_EN 0x1c10 819 #define ENCI_TST_MDSEL 0x1c11 820 #define ENCI_TST_Y 0x1c12 821 #define ENCI_TST_CB 0x1c13 822 #define ENCI_TST_CR 0x1c14 823 #define ENCI_TST_CLRBAR_STRT 0x1c15 824 #define ENCI_TST_CLRBAR_WIDTH 0x1c16 825 #define ENCI_TST_VDCNT_STSET 0x1c17 826 #define ENCI_VFIFO2VD_CTL 0x1c18 827 #define ENCI_VFIFO2VD_PIXEL_START 0x1c19 828 #define ENCI_VFIFO2VD_PIXEL_END 0x1c1a 829 #define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b 830 #define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c 831 #define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d 832 #define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e 833 #define ENCI_VFIFO2VD_CTL2 0x1c1f 834 #define ENCT_VFIFO2VD_CTL 0x1c20 835 #define ENCT_VFIFO2VD_PIXEL_START 0x1c21 836 #define ENCT_VFIFO2VD_PIXEL_END 0x1c22 837 #define ENCT_VFIFO2VD_LINE_TOP_START 0x1c23 838 #define ENCT_VFIFO2VD_LINE_TOP_END 0x1c24 839 #define ENCT_VFIFO2VD_LINE_BOT_START 0x1c25 840 #define ENCT_VFIFO2VD_LINE_BOT_END 0x1c26 841 #define ENCT_VFIFO2VD_CTL2 0x1c27 842 #define ENCT_TST_EN 0x1c28 843 #define ENCT_TST_MDSEL 0x1c29 844 #define ENCT_TST_Y 0x1c2a 845 #define ENCT_TST_CB 0x1c2b 846 #define ENCT_TST_CR 0x1c2c 847 #define ENCT_TST_CLRBAR_STRT 0x1c2d 848 #define ENCT_TST_CLRBAR_WIDTH 0x1c2e 849 #define ENCT_TST_VDCNT_STSET 0x1c2f 850 #define ENCP_DVI_HSO_BEGIN 0x1c30 851 #define ENCP_DVI_HSO_END 0x1c31 852 #define ENCP_DVI_VSO_BLINE_EVN 0x1c32 853 #define ENCP_DVI_VSO_BLINE_ODD 0x1c33 854 #define ENCP_DVI_VSO_ELINE_EVN 0x1c34 855 #define ENCP_DVI_VSO_ELINE_ODD 0x1c35 856 #define ENCP_DVI_VSO_BEGIN_EVN 0x1c36 857 #define ENCP_DVI_VSO_BEGIN_ODD 0x1c37 858 #define ENCP_DVI_VSO_END_EVN 0x1c38 859 #define ENCP_DVI_VSO_END_ODD 0x1c39 860 #define ENCP_DE_H_BEGIN 0x1c3a 861 #define ENCP_DE_H_END 0x1c3b 862 #define ENCP_DE_V_BEGIN_EVEN 0x1c3c 863 #define ENCP_DE_V_END_EVEN 0x1c3d 864 #define ENCP_DE_V_BEGIN_ODD 0x1c3e 865 #define ENCP_DE_V_END_ODD 0x1c3f 866 #define ENCI_SYNC_LINE_LENGTH 0x1c40 867 #define ENCI_SYNC_PIXEL_EN 0x1c41 868 #define ENCI_SYNC_TO_LINE_EN 0x1c42 869 #define ENCI_SYNC_TO_PIXEL 0x1c43 870 #define ENCP_SYNC_LINE_LENGTH 0x1c44 871 #define ENCP_SYNC_PIXEL_EN 0x1c45 872 #define ENCP_SYNC_TO_LINE_EN 0x1c46 873 #define ENCP_SYNC_TO_PIXEL 0x1c47 874 #define ENCT_SYNC_LINE_LENGTH 0x1c48 875 #define ENCT_SYNC_PIXEL_EN 0x1c49 876 #define ENCT_SYNC_TO_LINE_EN 0x1c4a 877 #define ENCT_SYNC_TO_PIXEL 0x1c4b 878 #define ENCL_SYNC_LINE_LENGTH 0x1c4c 879 #define ENCL_SYNC_PIXEL_EN 0x1c4d 880 #define ENCL_SYNC_TO_LINE_EN 0x1c4e 881 #define ENCL_SYNC_TO_PIXEL 0x1c4f 882 #define ENCP_VFIFO2VD_CTL2 0x1c50 883 #define VENC_DVI_SETTING_MORE 0x1c51 884 #define VENC_VDAC_DAC4_FILT_CTRL0 0x1c54 885 #define VENC_VDAC_DAC4_FILT_CTRL1 0x1c55 886 #define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56 887 #define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57 888 #define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58 889 #define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59 890 #define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a 891 #define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b 892 #define VENC_VDAC_DAC2_FILT_CTRL0 0x1c5c 893 #define VENC_VDAC_DAC2_FILT_CTRL1 0x1c5d 894 #define VENC_VDAC_DAC3_FILT_CTRL0 0x1c5e 895 #define VENC_VDAC_DAC3_FILT_CTRL1 0x1c5f 896 #define ENCT_VIDEO_EN 0x1c60 897 #define ENCT_VIDEO_Y_SCL 0x1c61 898 #define ENCT_VIDEO_PB_SCL 0x1c62 899 #define ENCT_VIDEO_PR_SCL 0x1c63 900 #define ENCT_VIDEO_Y_OFFST 0x1c64 901 #define ENCT_VIDEO_PB_OFFST 0x1c65 902 #define ENCT_VIDEO_PR_OFFST 0x1c66 903 #define ENCT_VIDEO_MODE 0x1c67 904 #define ENCT_VIDEO_MODE_ADV 0x1c68 905 #define ENCT_DBG_PX_RST 0x1c69 906 #define ENCT_DBG_LN_RST 0x1c6a 907 #define ENCT_DBG_PX_INT 0x1c6b 908 #define ENCT_DBG_LN_INT 0x1c6c 909 #define ENCT_VIDEO_YFP1_HTIME 0x1c6d 910 #define ENCT_VIDEO_YFP2_HTIME 0x1c6e 911 #define ENCT_VIDEO_YC_DLY 0x1c6f 912 #define ENCT_VIDEO_MAX_PXCNT 0x1c70 913 #define ENCT_VIDEO_HAVON_END 0x1c71 914 #define ENCT_VIDEO_HAVON_BEGIN 0x1c72 915 #define ENCT_VIDEO_VAVON_ELINE 0x1c73 916 #define ENCT_VIDEO_VAVON_BLINE 0x1c74 917 #define ENCT_VIDEO_HSO_BEGIN 0x1c75 918 #define ENCT_VIDEO_HSO_END 0x1c76 919 #define ENCT_VIDEO_VSO_BEGIN 0x1c77 920 #define ENCT_VIDEO_VSO_END 0x1c78 921 #define ENCT_VIDEO_VSO_BLINE 0x1c79 922 #define ENCT_VIDEO_VSO_ELINE 0x1c7a 923 #define ENCT_VIDEO_MAX_LNCNT 0x1c7b 924 #define ENCT_VIDEO_BLANKY_VAL 0x1c7c 925 #define ENCT_VIDEO_BLANKPB_VAL 0x1c7d 926 #define ENCT_VIDEO_BLANKPR_VAL 0x1c7e 927 #define ENCT_VIDEO_HOFFST 0x1c7f 928 #define ENCT_VIDEO_VOFFST 0x1c80 929 #define ENCT_VIDEO_RGB_CTRL 0x1c81 930 #define ENCT_VIDEO_FILT_CTRL 0x1c82 931 #define ENCT_VIDEO_OFLD_VPEQ_OFST 0x1c83 932 #define ENCT_VIDEO_OFLD_VOAV_OFST 0x1c84 933 #define ENCT_VIDEO_MATRIX_CB 0x1c85 934 #define ENCT_VIDEO_MATRIX_CR 0x1c86 935 #define ENCT_VIDEO_RGBIN_CTRL 0x1c87 936 #define ENCT_MAX_LINE_SWITCH_POINT 0x1c88 937 #define ENCT_DACSEL_0 0x1c89 938 #define ENCT_DACSEL_1 0x1c8a 939 #define ENCL_VFIFO2VD_CTL 0x1c90 940 #define ENCL_VFIFO2VD_PIXEL_START 0x1c91 941 #define ENCL_VFIFO2VD_PIXEL_END 0x1c92 942 #define ENCL_VFIFO2VD_LINE_TOP_START 0x1c93 943 #define ENCL_VFIFO2VD_LINE_TOP_END 0x1c94 944 #define ENCL_VFIFO2VD_LINE_BOT_START 0x1c95 945 #define ENCL_VFIFO2VD_LINE_BOT_END 0x1c96 946 #define ENCL_VFIFO2VD_CTL2 0x1c97 947 #define ENCL_TST_EN 0x1c98 948 #define ENCL_TST_MDSEL 0x1c99 949 #define ENCL_TST_Y 0x1c9a 950 #define ENCL_TST_CB 0x1c9b 951 #define ENCL_TST_CR 0x1c9c 952 #define ENCL_TST_CLRBAR_STRT 0x1c9d 953 #define ENCL_TST_CLRBAR_WIDTH 0x1c9e 954 #define ENCL_TST_VDCNT_STSET 0x1c9f 955 #define ENCL_VIDEO_EN 0x1ca0 956 #define ENCL_VIDEO_Y_SCL 0x1ca1 957 #define ENCL_VIDEO_PB_SCL 0x1ca2 958 #define ENCL_VIDEO_PR_SCL 0x1ca3 959 #define ENCL_VIDEO_Y_OFFST 0x1ca4 960 #define ENCL_VIDEO_PB_OFFST 0x1ca5 961 #define ENCL_VIDEO_PR_OFFST 0x1ca6 962 #define ENCL_VIDEO_MODE 0x1ca7 963 #define ENCL_VIDEO_MODE_ADV 0x1ca8 964 #define ENCL_DBG_PX_RST 0x1ca9 965 #define ENCL_DBG_LN_RST 0x1caa 966 #define ENCL_DBG_PX_INT 0x1cab 967 #define ENCL_DBG_LN_INT 0x1cac 968 #define ENCL_VIDEO_YFP1_HTIME 0x1cad 969 #define ENCL_VIDEO_YFP2_HTIME 0x1cae 970 #define ENCL_VIDEO_YC_DLY 0x1caf 971 #define ENCL_VIDEO_MAX_PXCNT 0x1cb0 972 #define ENCL_VIDEO_HAVON_END 0x1cb1 973 #define ENCL_VIDEO_HAVON_BEGIN 0x1cb2 974 #define ENCL_VIDEO_VAVON_ELINE 0x1cb3 975 #define ENCL_VIDEO_VAVON_BLINE 0x1cb4 976 #define ENCL_VIDEO_HSO_BEGIN 0x1cb5 977 #define ENCL_VIDEO_HSO_END 0x1cb6 978 #define ENCL_VIDEO_VSO_BEGIN 0x1cb7 979 #define ENCL_VIDEO_VSO_END 0x1cb8 980 #define ENCL_VIDEO_VSO_BLINE 0x1cb9 981 #define ENCL_VIDEO_VSO_ELINE 0x1cba 982 #define ENCL_VIDEO_MAX_LNCNT 0x1cbb 983 #define ENCL_VIDEO_BLANKY_VAL 0x1cbc 984 #define ENCL_VIDEO_BLANKPB_VAL 0x1cbd 985 #define ENCL_VIDEO_BLANKPR_VAL 0x1cbe 986 #define ENCL_VIDEO_HOFFST 0x1cbf 987 #define ENCL_VIDEO_VOFFST 0x1cc0 988 #define ENCL_VIDEO_RGB_CTRL 0x1cc1 989 #define ENCL_VIDEO_FILT_CTRL 0x1cc2 990 #define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3 991 #define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4 992 #define ENCL_VIDEO_MATRIX_CB 0x1cc5 993 #define ENCL_VIDEO_MATRIX_CR 0x1cc6 994 #define ENCL_VIDEO_RGBIN_CTRL 0x1cc7 995 #define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8 996 #define ENCL_DACSEL_0 0x1cc9 997 #define ENCL_DACSEL_1 0x1cca 998 #define RDMA_AHB_START_ADDR_MAN 0x1100 999 #define RDMA_AHB_END_ADDR_MAN 0x1101 1000 #define RDMA_AHB_START_ADDR_1 0x1102 1001 #define RDMA_AHB_END_ADDR_1 0x1103 1002 #define RDMA_AHB_START_ADDR_2 0x1104 1003 #define RDMA_AHB_END_ADDR_2 0x1105 1004 #define RDMA_AHB_START_ADDR_3 0x1106 1005 #define RDMA_AHB_END_ADDR_3 0x1107 1006 #define RDMA_AHB_START_ADDR_4 0x1108 1007 #define RDMA_AHB_END_ADDR_4 0x1109 1008 #define RDMA_AHB_START_ADDR_5 0x110a 1009 #define RDMA_AHB_END_ADDR_5 0x110b 1010 #define RDMA_AHB_START_ADDR_6 0x110c 1011 #define RDMA_AHB_END_ADDR_6 0x110d 1012 #define RDMA_AHB_START_ADDR_7 0x110e 1013 #define RDMA_AHB_END_ADDR_7 0x110f 1014 #define RDMA_ACCESS_AUTO 0x1110 1015 #define RDMA_ACCESS_AUTO2 0x1111 1016 #define RDMA_ACCESS_AUTO3 0x1112 1017 #define RDMA_ACCESS_MAN 0x1113 1018 #define RDMA_CTRL 0x1114 1019 #define RDMA_STATUS 0x1115 1020 #define RDMA_STATUS2 0x1116 1021 #define RDMA_STATUS3 0x1117 1022 #define L_GAMMA_CNTL_PORT 0x1400 1023 #define L_GAMMA_DATA_PORT 0x1401 1024 #define L_GAMMA_ADDR_PORT 0x1402 1025 #define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403 1026 #define L_RGB_BASE_ADDR 0x1405 1027 #define L_RGB_COEFF_ADDR 0x1406 1028 #define L_POL_CNTL_ADDR 0x1407 1029 #define L_DITH_CNTL_ADDR 0x1408 1030 #define L_GAMMA_PROBE_CTRL 0x1409 1031 #define L_GAMMA_PROBE_COLOR_L 0x140a 1032 #define L_GAMMA_PROBE_COLOR_H 0x140b 1033 #define L_GAMMA_PROBE_HL_COLOR 0x140c 1034 #define L_GAMMA_PROBE_POS_X 0x140d 1035 #define L_GAMMA_PROBE_POS_Y 0x140e 1036 #define L_STH1_HS_ADDR 0x1410 1037 #define L_STH1_HE_ADDR 0x1411 1038 #define L_STH1_VS_ADDR 0x1412 1039 #define L_STH1_VE_ADDR 0x1413 1040 #define L_STH2_HS_ADDR 0x1414 1041 #define L_STH2_HE_ADDR 0x1415 1042 #define L_STH2_VS_ADDR 0x1416 1043 #define L_STH2_VE_ADDR 0x1417 1044 #define L_OEH_HS_ADDR 0x1418 1045 #define L_OEH_HE_ADDR 0x1419 1046 #define L_OEH_VS_ADDR 0x141a 1047 #define L_OEH_VE_ADDR 0x141b 1048 #define L_VCOM_HSWITCH_ADDR 0x141c 1049 #define L_VCOM_VS_ADDR 0x141d 1050 #define L_VCOM_VE_ADDR 0x141e 1051 #define L_CPV1_HS_ADDR 0x141f 1052 #define L_CPV1_HE_ADDR 0x1420 1053 #define L_CPV1_VS_ADDR 0x1421 1054 #define L_CPV1_VE_ADDR 0x1422 1055 #define L_CPV2_HS_ADDR 0x1423 1056 #define L_CPV2_HE_ADDR 0x1424 1057 #define L_CPV2_VS_ADDR 0x1425 1058 #define L_CPV2_VE_ADDR 0x1426 1059 #define L_STV1_HS_ADDR 0x1427 1060 #define L_STV1_HE_ADDR 0x1428 1061 #define L_STV1_VS_ADDR 0x1429 1062 #define L_STV1_VE_ADDR 0x142a 1063 #define L_STV2_HS_ADDR 0x142b 1064 #define L_STV2_HE_ADDR 0x142c 1065 #define L_STV2_VS_ADDR 0x142d 1066 #define L_STV2_VE_ADDR 0x142e 1067 #define L_OEV1_HS_ADDR 0x142f 1068 #define L_OEV1_HE_ADDR 0x1430 1069 #define L_OEV1_VS_ADDR 0x1431 1070 #define L_OEV1_VE_ADDR 0x1432 1071 #define L_OEV2_HS_ADDR 0x1433 1072 #define L_OEV2_HE_ADDR 0x1434 1073 #define L_OEV2_VS_ADDR 0x1435 1074 #define L_OEV2_VE_ADDR 0x1436 1075 #define L_OEV3_HS_ADDR 0x1437 1076 #define L_OEV3_HE_ADDR 0x1438 1077 #define L_OEV3_VS_ADDR 0x1439 1078 #define L_OEV3_VE_ADDR 0x143a 1079 #define L_LCD_PWR_ADDR 0x143b 1080 #define L_LCD_PWM0_LO_ADDR 0x143c 1081 #define L_LCD_PWM0_HI_ADDR 0x143d 1082 #define L_LCD_PWM1_LO_ADDR 0x143e 1083 #define L_LCD_PWM1_HI_ADDR 0x143f 1084 #define L_INV_CNT_ADDR 0x1440 1085 #define L_TCON_MISC_SEL_ADDR 0x1441 1086 #define L_DUAL_PORT_CNTL_ADDR 0x1442 1087 #define MLVDS_CLK_CTL1_HI 0x1443 1088 #define MLVDS_CLK_CTL1_LO 0x1444 1089 #define L_TCON_DOUBLE_CTL 0x1449 1090 #define L_TCON_PATTERN_HI 0x144a 1091 #define L_TCON_PATTERN_LO 0x144b 1092 #define LDIM_BL_ADDR_PORT 0x144e 1093 #define LDIM_BL_DATA_PORT 0x144f 1094 #define L_DE_HS_ADDR 0x1451 1095 #define L_DE_HE_ADDR 0x1452 1096 #define L_DE_VS_ADDR 0x1453 1097 #define L_DE_VE_ADDR 0x1454 1098 #define L_HSYNC_HS_ADDR 0x1455 1099 #define L_HSYNC_HE_ADDR 0x1456 1100 #define L_HSYNC_VS_ADDR 0x1457 1101 #define L_HSYNC_VE_ADDR 0x1458 1102 #define L_VSYNC_HS_ADDR 0x1459 1103 #define L_VSYNC_HE_ADDR 0x145a 1104 #define L_VSYNC_VS_ADDR 0x145b 1105 #define L_VSYNC_VE_ADDR 0x145c 1106 #define L_LCD_MCU_CTL 0x145d 1107 #define DUAL_MLVDS_CTL 0x1460 1108 #define DUAL_MLVDS_LINE_START 0x1461 1109 #define DUAL_MLVDS_LINE_END 0x1462 1110 #define DUAL_MLVDS_PIXEL_W_START_L 0x1463 1111 #define DUAL_MLVDS_PIXEL_W_END_L 0x1464 1112 #define DUAL_MLVDS_PIXEL_W_START_R 0x1465 1113 #define DUAL_MLVDS_PIXEL_W_END_R 0x1466 1114 #define DUAL_MLVDS_PIXEL_R_START_L 0x1467 1115 #define DUAL_MLVDS_PIXEL_R_CNT_L 0x1468 1116 #define DUAL_MLVDS_PIXEL_R_START_R 0x1469 1117 #define DUAL_MLVDS_PIXEL_R_CNT_R 0x146a 1118 #define V_INVERSION_PIXEL 0x1470 1119 #define V_INVERSION_LINE 0x1471 1120 #define V_INVERSION_CONTROL 0x1472 1121 #define MLVDS2_CONTROL 0x1474 1122 #define MLVDS2_CONFIG_HI 0x1475 1123 #define MLVDS2_CONFIG_LO 0x1476 1124 #define MLVDS2_DUAL_GATE_WR_START 0x1477 1125 #define MLVDS2_DUAL_GATE_WR_END 0x1478 1126 #define MLVDS2_DUAL_GATE_RD_START 0x1479 1127 #define MLVDS2_DUAL_GATE_RD_END 0x147a 1128 #define MLVDS2_SECOND_RESET_CTL 0x147b 1129 #define MLVDS2_DUAL_GATE_CTL_HI 0x147c 1130 #define MLVDS2_DUAL_GATE_CTL_LO 0x147d 1131 #define MLVDS2_RESET_CONFIG_HI 0x147e 1132 #define MLVDS2_RESET_CONFIG_LO 0x147f 1133 #define GAMMA_CNTL_PORT 0x1480 1134 #define GAMMA_DATA_PORT 0x1481 1135 #define GAMMA_ADDR_PORT 0x1482 1136 #define GAMMA_VCOM_HSWITCH_ADDR 0x1483 1137 #define RGB_BASE_ADDR 0x1485 1138 #define RGB_COEFF_ADDR 0x1486 1139 #define POL_CNTL_ADDR 0x1487 1140 #define DITH_CNTL_ADDR 0x1488 1141 #define GAMMA_PROBE_CTRL 0x1489 1142 #define GAMMA_PROBE_COLOR_L 0x148a 1143 #define GAMMA_PROBE_COLOR_H 0x148b 1144 #define GAMMA_PROBE_HL_COLOR 0x148c 1145 #define GAMMA_PROBE_POS_X 0x148d 1146 #define GAMMA_PROBE_POS_Y 0x148e 1147 #define STH1_HS_ADDR 0x1490 1148 #define STH1_HE_ADDR 0x1491 1149 #define STH1_VS_ADDR 0x1492 1150 #define STH1_VE_ADDR 0x1493 1151 #define STH2_HS_ADDR 0x1494 1152 #define STH2_HE_ADDR 0x1495 1153 #define STH2_VS_ADDR 0x1496 1154 #define STH2_VE_ADDR 0x1497 1155 #define OEH_HS_ADDR 0x1498 1156 #define OEH_HE_ADDR 0x1499 1157 #define OEH_VS_ADDR 0x149a 1158 #define OEH_VE_ADDR 0x149b 1159 #define VCOM_HSWITCH_ADDR 0x149c 1160 #define VCOM_VS_ADDR 0x149d 1161 #define VCOM_VE_ADDR 0x149e 1162 #define CPV1_HS_ADDR 0x149f 1163 #define CPV1_HE_ADDR 0x14a0 1164 #define CPV1_VS_ADDR 0x14a1 1165 #define CPV1_VE_ADDR 0x14a2 1166 #define CPV2_HS_ADDR 0x14a3 1167 #define CPV2_HE_ADDR 0x14a4 1168 #define CPV2_VS_ADDR 0x14a5 1169 #define CPV2_VE_ADDR 0x14a6 1170 #define STV1_HS_ADDR 0x14a7 1171 #define STV1_HE_ADDR 0x14a8 1172 #define STV1_VS_ADDR 0x14a9 1173 #define STV1_VE_ADDR 0x14aa 1174 #define STV2_HS_ADDR 0x14ab 1175 #define STV2_HE_ADDR 0x14ac 1176 #define STV2_VS_ADDR 0x14ad 1177 #define STV2_VE_ADDR 0x14ae 1178 #define OEV1_HS_ADDR 0x14af 1179 #define OEV1_HE_ADDR 0x14b0 1180 #define OEV1_VS_ADDR 0x14b1 1181 #define OEV1_VE_ADDR 0x14b2 1182 #define OEV2_HS_ADDR 0x14b3 1183 #define OEV2_HE_ADDR 0x14b4 1184 #define OEV2_VS_ADDR 0x14b5 1185 #define OEV2_VE_ADDR 0x14b6 1186 #define OEV3_HS_ADDR 0x14b7 1187 #define OEV3_HE_ADDR 0x14b8 1188 #define OEV3_VS_ADDR 0x14b9 1189 #define OEV3_VE_ADDR 0x14ba 1190 #define LCD_PWR_ADDR 0x14bb 1191 #define LCD_PWM0_LO_ADDR 0x14bc 1192 #define LCD_PWM0_HI_ADDR 0x14bd 1193 #define LCD_PWM1_LO_ADDR 0x14be 1194 #define LCD_PWM1_HI_ADDR 0x14bf 1195 #define INV_CNT_ADDR 0x14c0 1196 #define TCON_MISC_SEL_ADDR 0x14c1 1197 #define DUAL_PORT_CNTL_ADDR 0x14c2 1198 #define MLVDS_CONTROL 0x14c3 1199 #define MLVDS_RESET_PATTERN_HI 0x14c4 1200 #define MLVDS_RESET_PATTERN_LO 0x14c5 1201 #define MLVDS_RESET_PATTERN_EXT 0x14c6 1202 #define MLVDS_CONFIG_HI 0x14c7 1203 #define MLVDS_CONFIG_LO 0x14c8 1204 #define TCON_DOUBLE_CTL 0x14c9 1205 #define TCON_PATTERN_HI 0x14ca 1206 #define TCON_PATTERN_LO 0x14cb 1207 #define TCON_CONTROL_HI 0x14cc 1208 #define TCON_CONTROL_LO 0x14cd 1209 #define LVDS_BLANK_DATA_HI 0x14ce 1210 #define LVDS_BLANK_DATA_LO 0x14cf 1211 #define LVDS_PACK_CNTL_ADDR 0x14d0 1212 #define DE_HS_ADDR 0x14d1 1213 #define DE_HE_ADDR 0x14d2 1214 #define DE_VS_ADDR 0x14d3 1215 #define DE_VE_ADDR 0x14d4 1216 #define HSYNC_HS_ADDR 0x14d5 1217 #define HSYNC_HE_ADDR 0x14d6 1218 #define HSYNC_VS_ADDR 0x14d7 1219 #define HSYNC_VE_ADDR 0x14d8 1220 #define VSYNC_HS_ADDR 0x14d9 1221 #define VSYNC_HE_ADDR 0x14da 1222 #define VSYNC_VS_ADDR 0x14db 1223 #define VSYNC_VE_ADDR 0x14dc 1224 #define LCD_MCU_CTL 0x14dd 1225 #define LCD_MCU_DATA_0 0x14de 1226 #define LCD_MCU_DATA_1 0x14df 1227 #define LVDS_GEN_CNTL 0x14e0 1228 #define LVDS_PHY_CNTL0 0x14e1 1229 #define LVDS_PHY_CNTL1 0x14e2 1230 #define LVDS_PHY_CNTL2 0x14e3 1231 #define LVDS_PHY_CNTL3 0x14e4 1232 #define LVDS_PHY_CNTL4 0x14e5 1233 #define LVDS_PHY_CNTL5 0x14e6 1234 #define LVDS_SRG_TEST 0x14e8 1235 #define LVDS_BIST_MUX0 0x14e9 1236 #define LVDS_BIST_MUX1 0x14ea 1237 #define LVDS_BIST_FIXED0 0x14eb 1238 #define LVDS_BIST_FIXED1 0x14ec 1239 #define LVDS_BIST_CNTL0 0x14ed 1240 #define LVDS_CLKB_CLKA 0x14ee 1241 #define LVDS_PHY_CLK_CNTL 0x14ef 1242 #define LVDS_SER_EN 0x14f0 1243 #define LVDS_PHY_CNTL6 0x14f1 1244 #define LVDS_PHY_CNTL7 0x14f2 1245 #define LVDS_PHY_CNTL8 0x14f3 1246 #define MLVDS_CLK_CTL0_HI 0x14f4 1247 #define MLVDS_CLK_CTL0_LO 0x14f5 1248 #define MLVDS_DUAL_GATE_WR_START 0x14f6 1249 #define MLVDS_DUAL_GATE_WR_END 0x14f7 1250 #define MLVDS_DUAL_GATE_RD_START 0x14f8 1251 #define MLVDS_DUAL_GATE_RD_END 0x14f9 1252 #define MLVDS_SECOND_RESET_CTL 0x14fa 1253 #define MLVDS_DUAL_GATE_CTL_HI 0x14fb 1254 #define MLVDS_DUAL_GATE_CTL_LO 0x14fc 1255 #define MLVDS_RESET_CONFIG_HI 0x14fd 1256 #define MLVDS_RESET_CONFIG_LO 0x14fe 1257 #define VPU_OSD1_MMC_CTRL 0x2701 1258 #define VPU_OSD2_MMC_CTRL 0x2702 1259 #define VPU_VD1_MMC_CTRL 0x2703 1260 #define VPU_VD2_MMC_CTRL 0x2704 1261 #define VPU_DI_IF1_MMC_CTRL 0x2705 1262 #define VPU_DI_MEM_MMC_CTRL 0x2706 1263 #define VPU_DI_INP_MMC_CTRL 0x2707 1264 #define VPU_DI_MTNRD_MMC_CTRL 0x2708 1265 #define VPU_DI_CHAN2_MMC_CTRL 0x2709 1266 #define VPU_DI_MTNWR_MMC_CTRL 0x270a 1267 #define VPU_DI_NRWR_MMC_CTRL 0x270b 1268 #define VPU_DI_DIWR_MMC_CTRL 0x270c 1269 #define VPU_VDIN0_MMC_CTRL 0x270d 1270 #define VPU_VDIN1_MMC_CTRL 0x270e 1271 #define VPU_BT656_MMC_CTRL 0x270f 1272 #define VPU_TVD3D_MMC_CTRL 0x2710 1273 #define VPU_TVDVBI_MMC_CTRL 0x2711 1274 #define VPU_TVDVBI_VSLATCH_ADDR 0x2712 1275 #define VPU_TVDVBI_WRRSP_ADDR 0x2713 1276 #define VPU_VDIN_PRE_ARB_CTRL 0x2714 1277 #define VPU_VDISP_PRE_ARB_CTRL 0x2715 1278 #define VPU_VPUARB2_PRE_ARB_CTRL 0x2716 1279 #define VPU_OSD3_MMC_CTRL 0x2717 1280 #define VPU_OSD4_MMC_CTRL 0x2718 1281 #define VPU_VD3_MMC_CTRL 0x2719 1282 #define VPU_VIU_VENC_MUX_CTRL 0x271a 1283 #define VIU1_SEL_VENC_MASK 0x3 1284 #define VIU1_SEL_VENC_ENCL 0 1285 #define VIU1_SEL_VENC_ENCI 1 1286 #define VIU1_SEL_VENC_ENCP 2 1287 #define VIU1_SEL_VENC_ENCT 3 1288 #define VIU2_SEL_VENC_MASK 0xc 1289 #define VIU2_SEL_VENC_ENCL 0 1290 #define VIU2_SEL_VENC_ENCI (1 << 2) 1291 #define VIU2_SEL_VENC_ENCP (2 << 2) 1292 #define VIU2_SEL_VENC_ENCT (3 << 2) 1293 #define VPU_HDMI_SETTING 0x271b 1294 #define ENCI_INFO_READ 0x271c 1295 #define ENCP_INFO_READ 0x271d 1296 #define ENCT_INFO_READ 0x271e 1297 #define ENCL_INFO_READ 0x271f 1298 #define VPU_SW_RESET 0x2720 1299 #define VPU_D2D3_MMC_CTRL 0x2721 1300 #define VPU_CONT_MMC_CTRL 0x2722 1301 #define VPU_CLK_GATE 0x2723 1302 #define VPU_RDMA_MMC_CTRL 0x2724 1303 #define VPU_MEM_PD_REG0 0x2725 1304 #define VPU_MEM_PD_REG1 0x2726 1305 #define VPU_HDMI_DATA_OVR 0x2727 1306 #define VPU_PROT1_MMC_CTRL 0x2728 1307 #define VPU_PROT2_MMC_CTRL 0x2729 1308 #define VPU_PROT3_MMC_CTRL 0x272a 1309 #define VPU_ARB4_V1_MMC_CTRL 0x272b 1310 #define VPU_ARB4_V2_MMC_CTRL 0x272c 1311 #define VPU_VPU_PWM_V0 0x2730 1312 #define VPU_VPU_PWM_V1 0x2731 1313 #define VPU_VPU_PWM_V2 0x2732 1314 #define VPU_VPU_PWM_V3 0x2733 1315 #define VPU_VPU_PWM_H0 0x2734 1316 #define VPU_VPU_PWM_H1 0x2735 1317 #define VPU_VPU_PWM_H2 0x2736 1318 #define VPU_VPU_PWM_H3 0x2737 1319 #define VPU_MISC_CTRL 0x2740 1320 #define VPU_ISP_GCLK_CTRL0 0x2741 1321 #define VPU_ISP_GCLK_CTRL1 0x2742 1322 #define VPU_HDMI_FMT_CTRL 0x2743 1323 #define VPU_VDIN_ASYNC_HOLD_CTRL 0x2743 1324 #define VPU_VDISP_ASYNC_HOLD_CTRL 0x2744 1325 #define VPU_VPUARB2_ASYNC_HOLD_CTRL 0x2745 1326 1327 #define VPU_PROT1_CLK_GATE 0x2750 1328 #define VPU_PROT1_GEN_CNTL 0x2751 1329 #define VPU_PROT1_X_START_END 0x2752 1330 #define VPU_PROT1_Y_START_END 0x2753 1331 #define VPU_PROT1_Y_LEN_STEP 0x2754 1332 #define VPU_PROT1_RPT_LOOP 0x2755 1333 #define VPU_PROT1_RPT_PAT 0x2756 1334 #define VPU_PROT1_DDR 0x2757 1335 #define VPU_PROT1_RBUF_ROOM 0x2758 1336 #define VPU_PROT1_STAT_0 0x2759 1337 #define VPU_PROT1_STAT_1 0x275a 1338 #define VPU_PROT1_STAT_2 0x275b 1339 #define VPU_PROT1_REQ_ONOFF 0x275c 1340 #define VPU_PROT2_CLK_GATE 0x2760 1341 #define VPU_PROT2_GEN_CNTL 0x2761 1342 #define VPU_PROT2_X_START_END 0x2762 1343 #define VPU_PROT2_Y_START_END 0x2763 1344 #define VPU_PROT2_Y_LEN_STEP 0x2764 1345 #define VPU_PROT2_RPT_LOOP 0x2765 1346 #define VPU_PROT2_RPT_PAT 0x2766 1347 #define VPU_PROT2_DDR 0x2767 1348 #define VPU_PROT2_RBUF_ROOM 0x2768 1349 #define VPU_PROT2_STAT_0 0x2769 1350 #define VPU_PROT2_STAT_1 0x276a 1351 #define VPU_PROT2_STAT_2 0x276b 1352 #define VPU_PROT2_REQ_ONOFF 0x276c 1353 #define VPU_PROT3_CLK_GATE 0x2770 1354 #define VPU_PROT3_GEN_CNTL 0x2771 1355 #define VPU_PROT3_X_START_END 0x2772 1356 #define VPU_PROT3_Y_START_END 0x2773 1357 #define VPU_PROT3_Y_LEN_STEP 0x2774 1358 #define VPU_PROT3_RPT_LOOP 0x2775 1359 #define VPU_PROT3_RPT_PAT 0x2776 1360 #define VPU_PROT3_DDR 0x2777 1361 #define VPU_PROT3_RBUF_ROOM 0x2778 1362 #define VPU_PROT3_STAT_0 0x2779 1363 #define VPU_PROT3_STAT_1 0x277a 1364 #define VPU_PROT3_STAT_2 0x277b 1365 #define VPU_PROT3_REQ_ONOFF 0x277c 1366 #define VPU_RDARB_MODE_L1C1 0x2790 1367 #define VPU_RDARB_MODE_L1C2 0x2799 1368 #define VPU_RDARB_MODE_L2C1 0x279d 1369 #define VPU_WRARB_MODE_L2C1 0x27a2 1370 1371 /* osd super scale */ 1372 #define OSDSR_HV_SIZEIN 0x3130 1373 #define OSDSR_CTRL_MODE 0x3131 1374 #define OSDSR_ABIC_HCOEF 0x3132 1375 #define OSDSR_YBIC_HCOEF 0x3133 1376 #define OSDSR_CBIC_HCOEF 0x3134 1377 #define OSDSR_ABIC_VCOEF 0x3135 1378 #define OSDSR_YBIC_VCOEF 0x3136 1379 #define OSDSR_CBIC_VCOEF 0x3137 1380 #define OSDSR_VAR_PARA 0x3138 1381 #define OSDSR_CONST_PARA 0x3139 1382 #define OSDSR_RKE_EXTWIN 0x313a 1383 #define OSDSR_UK_GRAD2DDIAG_TH_RATE 0x313b 1384 #define OSDSR_UK_GRAD2DDIAG_LIMIT 0x313c 1385 #define OSDSR_UK_GRAD2DADJA_TH_RATE 0x313d 1386 #define OSDSR_UK_GRAD2DADJA_LIMIT 0x313e 1387 #define OSDSR_UK_BST_GAIN 0x313f 1388 #define OSDSR_HVBLEND_TH 0x3140 1389 #define OSDSR_DEMO_WIND_TB 0x3141 1390 #define OSDSR_DEMO_WIND_LR 0x3142 1391 #define OSDSR_INT_BLANK_NUM 0x3143 1392 #define OSDSR_FRM_END_STAT 0x3144 1393 #define OSDSR_ABIC_HCOEF0 0x3145 1394 #define OSDSR_YBIC_HCOEF0 0x3146 1395 #define OSDSR_CBIC_HCOEF0 0x3147 1396 #define OSDSR_ABIC_VCOEF0 0x3148 1397 #define OSDSR_YBIC_VCOEF0 0x3149 1398 #define OSDSR_CBIC_VCOEF0 0x314a 1399 1400 #endif /* __MESON_REGISTERS_H */ 1401
