Searched refs:LVL2_CLK_GATE_OVRE (Results 1 – 2 of 2) sorted by relevance
44 #define LVL2_CLK_GATE_OVRE 0x554 macro87 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()88 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()90 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable()
242 #define LVL2_CLK_GATE_OVRE 0x554 macro586 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war()587 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war()591 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war()620 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); in tegra210_vic_mbist_war()621 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE); in tegra210_vic_mbist_war()632 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); in tegra210_vic_mbist_war()643 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); in tegra210_ape_mbist_war()646 clk_base + LVL2_CLK_GATE_OVRE); in tegra210_ape_mbist_war()667 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); in tegra210_ape_mbist_war()[all …]
