| /Linux-v4.19/arch/c6x/lib/ |
| D | csum_64plus.S | 54 || ADD .L1 A16,A9,A9
67 || MVK .L1 1,A2
77 ADD .L1 A16,A9,A9
80 || ADD .L1 A8,A9,A9
87 ZERO .L1 A7
119 || ZERO .L1 A7
207 || ADD .L1 A3,A5,A5
297 MV .L1 A0,A3
314 MVK .L1 2,A0
315 AND .L1 A4,A0,A0
[all …]
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| /Linux-v4.19/arch/arc/kernel/ |
| D | entry-compact.S | 155 ; if L2 IRQ interrupted a L1 ISR, disable preemption
157 ; This is to avoid a potential L1-L2-L1 scenario
158 ; -L1 IRQ taken
159 ; -L2 interrupts L1 (before L1 ISR could run)
163 ; But both L1 and L2 re-enabled, so another L1 can be taken
164 ; while prev L1 is still unserviced
168 ; L2 interrupting L1 implies both L2 and L1 active
170 ; need to check STATUS32_L2 to determine if L1 was active
173 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
338 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
[all …]
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| /Linux-v4.19/security/apparmor/include/ |
| D | perms.h | 126 #define xcheck_ns_labels(L1, L2, FN, args...) \ argument
129 fn_for_each((L1), __p1, FN(__p1, (L2), args)); \
133 #define xcheck_labels_profiles(L1, L2, FN, args...) \ argument
134 xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
136 #define xcheck_labels(L1, L2, P, FN1, FN2) \ argument
137 xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
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| D | label.h | 168 #define next_comb(I, L1, L2) \ argument
179 #define label_for_each_comb(I, L1, L2, P1, P2) \ argument
181 ((P1) = (L1)->vec[(I).i]) && ((P2) = (L2)->vec[(I).j]); \
182 (I) = next_comb(I, L1, L2))
184 #define fn_for_each_comb(L1, L2, P1, P2, FN) \ argument
188 label_for_each_comb(i, (L1), (L2), (P1), (P2)) { \
248 #define fn_for_each2_XXX(L1, L2, P, FN, ...) \ argument
252 label_for_each ## __VA_ARGS__(i, (L1), (L2), (P)) { \
258 #define fn_for_each_in_merge(L1, L2, P, FN) \ argument
259 fn_for_each2_XXX((L1), (L2), P, FN, _in_merge)
[all …]
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| /Linux-v4.19/arch/arm/mm/ |
| D | proc-xsc3.S | 71 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
199 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
227 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
248 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
253 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
272 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
[all …]
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| /Linux-v4.19/arch/powerpc/perf/ |
| D | power8-pmu.c | 136 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
137 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
139 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
140 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
141 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
142 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
143 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
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| D | power9-pmu.c | 172 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
173 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
174 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
175 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
176 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
177 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
178 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
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| /Linux-v4.19/arch/riscv/lib/ |
| D | udivdi3.S | 22 .L1: label
26 bgtu a1, a2, .L1
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| D | tishift.S | 15 beqz a2, .L1
32 .L1: label
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| /Linux-v4.19/arch/hexagon/lib/ |
| D | memset.S | 172 if (r2==#0) jump:nt .L1
199 if (p1) jump .L1
210 if (p0.new) jump:nt .L1
221 if (p0.new) jump:nt .L1
297 .L1: label
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| /Linux-v4.19/Documentation/driver-api/ |
| D | edac.rst | 145 - CPU caches (L1 and L2)
155 For example, a cache could be composed of L1, L2 and L3 levels of cache.
156 Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
164 cpu/cpu0/.. <L1 and L2 block directory>
165 /L1-cache/ce_count
169 cpu/cpu1/.. <L1 and L2 block directory>
170 /L1-cache/ce_count
176 the L1 and L2 directories would be "edac_device_block's"
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| /Linux-v4.19/arch/c6x/kernel/ |
| D | head.S | 61 CMPEQ .L1 A10,A0,A0
84 L1: BNOP .S2 L1,5 label
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| /Linux-v4.19/drivers/pci/pcie/ |
| D | Kconfig | 73 state L0/L0s/L1.
107 Enable PCI Express ASPM L0s and L1 where possible, even if the
114 Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
115 possible. This would result in higher power savings while staying in L1
122 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
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| /Linux-v4.19/arch/m68k/fpsp040/ |
| D | setox.S | 104 | 3.1 R := X + N*L1, where L1 := single-precision(-log2/64).
105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
108 | b) N*L1 is exact because N is no longer than 22 bits and
109 | L1 is no longer than 24 bits.
110 | c) The calculation X+N*L1 is also exact due to cancellation.
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
505 fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64)
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
507 faddx %fp1,%fp0 | ...X + N*L1
[all …]
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| /Linux-v4.19/arch/powerpc/boot/dts/ |
| D | sbc8548-pre.dtsi | 38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
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| /Linux-v4.19/arch/m68k/lib/ |
| D | divsi3.S | 95 jpl L1
102 L1: movel sp@(8), d0 /* d0 = dividend */ label
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| /Linux-v4.19/Documentation/devicetree/bindings/media/ |
| D | st-rc.txt | 10 - rx-mode: can be "infrared" or "uhf". This property specifies the L1
13 - tx-mode: should be "infrared". This property specifies the L1
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| /Linux-v4.19/tools/perf/Documentation/ |
| D | perf-c2c.txt | 169 L1Hit - store accesses that hit L1
170 L1Hit - store accesses that missed L1
181 Core Load Hit - FB, L1, L2
182 - count of load hits in FB (Fill Buffer), L1 and L2 cache
192 Store Refs - L1 Hit, L1 Miss
193 - % of store accesses that hit/missed L1 for given offset within cacheline
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| /Linux-v4.19/arch/alpha/boot/ |
| D | bootp.c | 66 #define L1 ((unsigned long *) 0x200802000) macro
78 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| D | main.c | 60 #define L1 ((unsigned long *) 0x200802000) macro
72 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| /Linux-v4.19/Documentation/translations/zh_CN/arm64/ |
| D | memory.txt | 90 | | +---------------------> [38:30] L1 索引
105 | +-------------------------------> [47:42] L1 索引
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| /Linux-v4.19/arch/arm/mach-omap2/ |
| D | sram243x.S | 53 str r3, [r2] @ go to L1-freq operation
56 mov r9, #0x1 @ set up for L1 voltage call
115 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
119 str r5, [r4] @ Force transition to L1
210 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
214 str r8, [r10] @ Force transition to L1
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| D | sram242x.S | 53 str r3, [r2] @ go to L1-freq operation
56 mov r9, #0x1 @ set up for L1 voltage call
115 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
119 str r5, [r4] @ Force transition to L1
210 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
214 str r8, [r10] @ Force transition to L1
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| /Linux-v4.19/Documentation/locking/ |
| D | rt-mutex-design.txt | 46 grab lock L1 (owned by C)
129 Mutexes: L1, L2, L3, L4
131 A owns: L1
132 B blocked on L1
142 E->L4->D->L3->C->L2->B->L1->A
149 F->L5->B->L1->A
158 +->B->L1->A
170 G->L2->B->L1->A
178 G-+ +->B->L1->A
220 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
[all …]
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| /Linux-v4.19/tools/perf/util/ |
| D | parse-events.l | 338 L1-dcache|l1-d|l1d|L1-data |
339 L1-icache|l1-i|l1i|L1-instruction |
|
