Searched refs:KSEG1 (Results 1 – 13 of 13) sorted by relevance
33 #define JMR3927_PORT_BASE KSEG136 #define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)37 #define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)38 #define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)39 #define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)40 #define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
36 #define FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))37 #define FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))38 #define FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
81 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)89 #define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)99 #define KSEG1 0xa0000000 macro
27 #define BOOT_REG_BASE (KSEG1 | 0x1F200000)33 #define WDT_REG_BASE (KSEG1 | 0x1F8803F0)
36 #define BOOT_REG_BASE (KSEG1 | 0x1F200000)
54 set_io_port_base(KSEG1); in plat_mem_setup()
50 set_io_port_base(KSEG1); in plat_mem_setup()
96 #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
80 set_io_port_base((unsigned long) KSEG1); in plat_mem_setup()
71 set_io_port_base(KSEG1); in plat_mem_setup()
110 set_io_port_base(KSEG1); in prom_init()
229 set_io_port_base(KSEG1); in plat_mem_setup()
224 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); in rbtx4927_mem_setup()
