Searched refs:JZ4740_CLK_PLL (Results 1 – 2 of 2) sorted by relevance
| /Linux-v4.19/drivers/clk/ingenic/ |
| D | jz4740-cgu.c | 67 [JZ4740_CLK_PLL] = {
92 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
98 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
104 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
110 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
116 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
143 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
281 cppcr &= ~BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit); in jz4740_clock_suspend()
290 cppcr |= BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit); in jz4740_clock_resume()
293 stable = BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.stable_bit); in jz4740_clock_resume()
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| /Linux-v4.19/include/dt-bindings/clock/ |
| D | jz4740-cgu.h | 17 #define JZ4740_CLK_PLL 2 macro
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