1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 65 #ifndef __iwl_fw_api_rx_h__ 66 #define __iwl_fw_api_rx_h__ 67 68 /* API for pre-9000 hardware */ 69 70 #define IWL_RX_INFO_PHY_CNT 8 71 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 72 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 73 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 74 #define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 75 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 76 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 77 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 78 79 enum iwl_mac_context_info { 80 MAC_CONTEXT_INFO_NONE, 81 MAC_CONTEXT_INFO_GSCAN, 82 }; 83 84 /** 85 * struct iwl_rx_phy_info - phy info 86 * (REPLY_RX_PHY_CMD = 0xc0) 87 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 88 * @cfg_phy_cnt: configurable DSP phy data byte count 89 * @stat_id: configurable DSP phy data set ID 90 * @reserved1: reserved 91 * @system_timestamp: GP2 at on air rise 92 * @timestamp: TSF at on air rise 93 * @beacon_time_stamp: beacon at on-air rise 94 * @phy_flags: general phy flags: band, modulation, ... 95 * @channel: channel number 96 * @non_cfg_phy: for various implementations of non_cfg_phy 97 * @rate_n_flags: RATE_MCS_* 98 * @byte_count: frame's byte-count 99 * @frame_time: frame's time on the air, based on byte count and frame rate 100 * calculation 101 * @mac_active_msk: what MACs were active when the frame was received 102 * @mac_context_info: additional info on the context in which the frame was 103 * received as defined in &enum iwl_mac_context_info 104 * 105 * Before each Rx, the device sends this data. It contains PHY information 106 * about the reception of the packet. 107 */ 108 struct iwl_rx_phy_info { 109 u8 non_cfg_phy_cnt; 110 u8 cfg_phy_cnt; 111 u8 stat_id; 112 u8 reserved1; 113 __le32 system_timestamp; 114 __le64 timestamp; 115 __le32 beacon_time_stamp; 116 __le16 phy_flags; 117 __le16 channel; 118 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 119 __le32 rate_n_flags; 120 __le32 byte_count; 121 u8 mac_active_msk; 122 u8 mac_context_info; 123 __le16 frame_time; 124 } __packed; 125 126 /* 127 * TCP offload Rx assist info 128 * 129 * bits 0:3 - reserved 130 * bits 4:7 - MIC CRC length 131 * bits 8:12 - MAC header length 132 * bit 13 - Padding indication 133 * bit 14 - A-AMSDU indication 134 * bit 15 - Offload enabled 135 */ 136 enum iwl_csum_rx_assist_info { 137 CSUM_RXA_RESERVED_MASK = 0x000f, 138 CSUM_RXA_MICSIZE_MASK = 0x00f0, 139 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 140 CSUM_RXA_PADD = BIT(13), 141 CSUM_RXA_AMSDU = BIT(14), 142 CSUM_RXA_ENA = BIT(15) 143 }; 144 145 /** 146 * struct iwl_rx_mpdu_res_start - phy info 147 * @byte_count: byte count of the frame 148 * @assist: see &enum iwl_csum_rx_assist_info 149 */ 150 struct iwl_rx_mpdu_res_start { 151 __le16 byte_count; 152 __le16 assist; 153 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 154 155 /** 156 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 157 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 158 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 159 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 160 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 161 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 162 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 163 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 164 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 165 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 166 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 167 */ 168 enum iwl_rx_phy_flags { 169 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 170 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 171 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 172 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 173 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 174 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 175 RX_RES_PHY_FLAGS_AGG = BIT(7), 176 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 177 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 178 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 179 }; 180 181 /** 182 * enum iwl_mvm_rx_status - written by fw for each Rx packet 183 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 184 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 185 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 186 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 187 * @RX_MPDU_RES_STATUS_KEY_PARAM_OK: key parameters were usable 188 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 189 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 190 * in the driver. 191 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 192 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 193 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 194 * %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 195 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 196 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 197 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 198 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 199 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 200 * algorithm 201 * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 202 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 203 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 204 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 205 * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: extended IV (set with TKIP) 206 * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: key ID comparison done 207 * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 208 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 209 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 210 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 211 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 212 * @RX_MPDU_RES_STATUS_FILTERING_MSK: filter status 213 * @RX_MPDU_RES_STATUS2_FILTERING_MSK: filter status 2 214 */ 215 enum iwl_mvm_rx_status { 216 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 217 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 218 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 219 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 220 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4), 221 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 222 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 223 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 224 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 225 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 226 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 227 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 228 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 229 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 230 RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 231 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 232 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 233 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 234 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13), 235 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14), 236 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15), 237 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 238 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 239 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 240 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 241 RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 242 RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 243 }; 244 245 /* 9000 series API */ 246 enum iwl_rx_mpdu_mac_flags1 { 247 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 248 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 249 /* shift should be 4, but the length is measured in 2-byte 250 * words, so shifting only by 3 gives a byte result 251 */ 252 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 253 }; 254 255 enum iwl_rx_mpdu_mac_flags2 { 256 /* in 2-byte words */ 257 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 258 IWL_RX_MPDU_MFLG2_PAD = 0x20, 259 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 260 }; 261 262 enum iwl_rx_mpdu_amsdu_info { 263 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 264 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 265 }; 266 267 enum iwl_rx_l3_proto_values { 268 IWL_RX_L3_TYPE_NONE, 269 IWL_RX_L3_TYPE_IPV4, 270 IWL_RX_L3_TYPE_IPV4_FRAG, 271 IWL_RX_L3_TYPE_IPV6_FRAG, 272 IWL_RX_L3_TYPE_IPV6, 273 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 274 IWL_RX_L3_TYPE_ARP, 275 IWL_RX_L3_TYPE_EAPOL, 276 }; 277 278 #define IWL_RX_L3_PROTO_POS 4 279 280 enum iwl_rx_l3l4_flags { 281 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 282 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 283 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 284 IWL_RX_L3L4_TCP_ACK = BIT(3), 285 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 286 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 287 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 288 }; 289 290 enum iwl_rx_mpdu_status { 291 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 292 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 293 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 294 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 295 IWL_RX_MPDU_STATUS_KEY_PARAM_OK = BIT(4), 296 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 297 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 298 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 299 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 300 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 301 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 302 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 303 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 304 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 305 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 306 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 307 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 308 IWL_RX_MPDU_STATUS_WEP_MATCH = BIT(12), 309 IWL_RX_MPDU_STATUS_EXT_IV_MATCH = BIT(13), 310 IWL_RX_MPDU_STATUS_KEY_ID_MATCH = BIT(14), 311 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 312 }; 313 314 enum iwl_rx_mpdu_hash_filter { 315 IWL_RX_MPDU_HF_A1_HASH_MASK = 0x3f, 316 IWL_RX_MPDU_HF_FILTER_STATUS_MASK = 0xc0, 317 }; 318 319 enum iwl_rx_mpdu_sta_id_flags { 320 IWL_RX_MPDU_SIF_STA_ID_MASK = 0x1f, 321 IWL_RX_MPDU_SIF_RRF_ABORT = 0x20, 322 IWL_RX_MPDU_SIF_FILTER_STATUS_MASK = 0xc0, 323 }; 324 325 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 326 327 enum iwl_rx_mpdu_reorder_data { 328 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 329 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 330 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 331 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 332 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 333 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 334 }; 335 336 enum iwl_rx_mpdu_phy_info { 337 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 338 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 339 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 340 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 341 }; 342 343 enum iwl_rx_mpdu_mac_info { 344 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 345 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 346 }; 347 348 /* 349 * enum iwl_rx_he_phy - HE PHY data 350 */ 351 enum iwl_rx_he_phy { 352 IWL_RX_HE_PHY_BEAM_CHNG = BIT(0), 353 IWL_RX_HE_PHY_UPLINK = BIT(1), 354 IWL_RX_HE_PHY_BSS_COLOR_MASK = 0xfc, 355 IWL_RX_HE_PHY_SPATIAL_REUSE_MASK = 0xf00, 356 IWL_RX_HE_PHY_SU_EXT_BW10 = BIT(12), 357 IWL_RX_HE_PHY_TXOP_DUR_MASK = 0xfe000, 358 IWL_RX_HE_PHY_LDPC_EXT_SYM = BIT(20), 359 IWL_RX_HE_PHY_PRE_FEC_PAD_MASK = 0x600000, 360 IWL_RX_HE_PHY_PE_DISAMBIG = BIT(23), 361 IWL_RX_HE_PHY_DOPPLER = BIT(24), 362 /* 6 bits reserved */ 363 IWL_RX_HE_PHY_DELIM_EOF = BIT(31), 364 365 /* second dword - MU data */ 366 IWL_RX_HE_PHY_SIGB_COMPRESSION = BIT_ULL(32 + 0), 367 IWL_RX_HE_PHY_SIBG_SYM_OR_USER_NUM_MASK = 0x1e00000000ULL, 368 IWL_RX_HE_PHY_HE_LTF_NUM_MASK = 0xe000000000ULL, 369 IWL_RX_HE_PHY_RU_ALLOC_SEC80 = BIT_ULL(32 + 8), 370 /* trigger encoded */ 371 IWL_RX_HE_PHY_RU_ALLOC_MASK = 0xfe0000000000ULL, 372 IWL_RX_HE_PHY_SIGB_MCS_MASK = 0xf000000000000ULL, 373 /* 1 bit reserved */ 374 IWL_RX_HE_PHY_SIGB_DCM = BIT_ULL(32 + 21), 375 IWL_RX_HE_PHY_PREAMBLE_PUNC_TYPE_MASK = 0xc0000000000000ULL, 376 /* 8 bits reserved */ 377 }; 378 379 /** 380 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 381 */ 382 struct iwl_rx_mpdu_desc_v1 { 383 /* DW7 - carries rss_hash only when rpa_en == 1 */ 384 /** 385 * @rss_hash: RSS hash value 386 */ 387 __le32 rss_hash; 388 /* DW8 - carries filter_match only when rpa_en == 1 */ 389 /** 390 * @filter_match: filter match value 391 */ 392 __le32 filter_match; 393 /* DW9 */ 394 /** 395 * @rate_n_flags: RX rate/flags encoding 396 */ 397 __le32 rate_n_flags; 398 /* DW10 */ 399 /** 400 * @energy_a: energy chain A 401 */ 402 u8 energy_a; 403 /** 404 * @energy_b: energy chain B 405 */ 406 u8 energy_b; 407 /** 408 * @channel: channel number 409 */ 410 u8 channel; 411 /** 412 * @mac_context: MAC context mask 413 */ 414 u8 mac_context; 415 /* DW11 */ 416 /** 417 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 418 */ 419 __le32 gp2_on_air_rise; 420 /* DW12 & DW13 */ 421 union { 422 /** 423 * @tsf_on_air_rise: 424 * TSF value on air rise (INA), only valid if 425 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 426 */ 427 __le64 tsf_on_air_rise; 428 /** 429 * @he_phy_data: 430 * HE PHY data, see &enum iwl_rx_he_phy, valid 431 * only if %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set 432 */ 433 __le64 he_phy_data; 434 }; 435 } __packed; 436 437 /** 438 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 439 */ 440 struct iwl_rx_mpdu_desc_v3 { 441 /* DW7 - carries filter_match only when rpa_en == 1 */ 442 /** 443 * @filter_match: filter match value 444 */ 445 __le32 filter_match; 446 /* DW8 - carries rss_hash only when rpa_en == 1 */ 447 /** 448 * @rss_hash: RSS hash value 449 */ 450 __le32 rss_hash; 451 /* DW9 */ 452 /** 453 * @partial_hash: 31:0 ip/tcp header hash 454 * w/o some fields (such as IP SRC addr) 455 */ 456 __le32 partial_hash; 457 /* DW10 */ 458 /** 459 * @raw_xsum: raw xsum value 460 */ 461 __le32 raw_xsum; 462 /* DW11 */ 463 /** 464 * @rate_n_flags: RX rate/flags encoding 465 */ 466 __le32 rate_n_flags; 467 /* DW12 */ 468 /** 469 * @energy_a: energy chain A 470 */ 471 u8 energy_a; 472 /** 473 * @energy_b: energy chain B 474 */ 475 u8 energy_b; 476 /** 477 * @channel: channel number 478 */ 479 u8 channel; 480 /** 481 * @mac_context: MAC context mask 482 */ 483 u8 mac_context; 484 /* DW13 */ 485 /** 486 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 487 */ 488 __le32 gp2_on_air_rise; 489 /* DW14 & DW15 */ 490 union { 491 /** 492 * @tsf_on_air_rise: 493 * TSF value on air rise (INA), only valid if 494 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 495 */ 496 __le64 tsf_on_air_rise; 497 /** 498 * @he_phy_data: 499 * HE PHY data, see &enum iwl_rx_he_phy, valid 500 * only if %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set 501 */ 502 __le64 he_phy_data; 503 }; 504 /* DW16 & DW17 */ 505 /** 506 * @reserved: reserved 507 */ 508 __le32 reserved[2]; 509 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */ 510 511 /** 512 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 513 */ 514 struct iwl_rx_mpdu_desc { 515 /* DW2 */ 516 /** 517 * @mpdu_len: MPDU length 518 */ 519 __le16 mpdu_len; 520 /** 521 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 522 */ 523 u8 mac_flags1; 524 /** 525 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 526 */ 527 u8 mac_flags2; 528 /* DW3 */ 529 /** 530 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 531 */ 532 u8 amsdu_info; 533 /** 534 * @phy_info: &enum iwl_rx_mpdu_phy_info 535 */ 536 __le16 phy_info; 537 /** 538 * @mac_phy_idx: MAC/PHY index 539 */ 540 u8 mac_phy_idx; 541 /* DW4 - carries csum data only when rpa_en == 1 */ 542 /** 543 * @raw_csum: raw checksum (alledgedly unreliable) 544 */ 545 __le16 raw_csum; 546 /** 547 * @l3l4_flags: &enum iwl_rx_l3l4_flags 548 */ 549 __le16 l3l4_flags; 550 /* DW5 */ 551 /** 552 * @status: &enum iwl_rx_mpdu_status 553 */ 554 __le16 status; 555 /** 556 * @hash_filter: hash filter value 557 */ 558 u8 hash_filter; 559 /** 560 * @sta_id_flags: &enum iwl_rx_mpdu_sta_id_flags 561 */ 562 u8 sta_id_flags; 563 /* DW6 */ 564 /** 565 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 566 */ 567 __le32 reorder_data; 568 569 union { 570 struct iwl_rx_mpdu_desc_v1 v1; 571 struct iwl_rx_mpdu_desc_v3 v3; 572 }; 573 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */ 574 575 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 576 577 struct iwl_frame_release { 578 u8 baid; 579 u8 reserved; 580 __le16 nssn; 581 }; 582 583 enum iwl_rss_hash_func_en { 584 IWL_RSS_HASH_TYPE_IPV4_TCP, 585 IWL_RSS_HASH_TYPE_IPV4_UDP, 586 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 587 IWL_RSS_HASH_TYPE_IPV6_TCP, 588 IWL_RSS_HASH_TYPE_IPV6_UDP, 589 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 590 }; 591 592 #define IWL_RSS_HASH_KEY_CNT 10 593 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 594 #define IWL_RSS_ENABLE 1 595 596 /** 597 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 598 * 599 * @flags: 1 - enable, 0 - disable 600 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 601 * @reserved: reserved 602 * @secret_key: 320 bit input of random key configuration from driver 603 * @indirection_table: indirection table 604 */ 605 struct iwl_rss_config_cmd { 606 __le32 flags; 607 u8 hash_mask; 608 u8 reserved[3]; 609 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 610 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 611 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 612 613 #define IWL_MULTI_QUEUE_SYNC_MSG_MAX_SIZE 128 614 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 615 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 616 617 /** 618 * struct iwl_rxq_sync_cmd - RXQ notification trigger 619 * 620 * @flags: flags of the notification. bit 0:3 are the sender queue 621 * @rxq_mask: rx queues to send the notification on 622 * @count: number of bytes in payload, should be DWORD aligned 623 * @payload: data to send to rx queues 624 */ 625 struct iwl_rxq_sync_cmd { 626 __le32 flags; 627 __le32 rxq_mask; 628 __le32 count; 629 u8 payload[]; 630 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 631 632 /** 633 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 634 * sync command 635 * 636 * @count: number of bytes in payload 637 * @payload: data to send to rx queues 638 */ 639 struct iwl_rxq_sync_notification { 640 __le32 count; 641 u8 payload[]; 642 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 643 644 /** 645 * enum iwl_mvm_rxq_notif_type - Internal message identifier 646 * 647 * @IWL_MVM_RXQ_EMPTY: empty sync notification 648 * @IWL_MVM_RXQ_NOTIF_DEL_BA: notify RSS queues of delBA 649 */ 650 enum iwl_mvm_rxq_notif_type { 651 IWL_MVM_RXQ_EMPTY, 652 IWL_MVM_RXQ_NOTIF_DEL_BA, 653 }; 654 655 /** 656 * struct iwl_mvm_internal_rxq_notif - Internal representation of the data sent 657 * in &iwl_rxq_sync_cmd. Should be DWORD aligned. 658 * FW is agnostic to the payload, so there are no endianity requirements. 659 * 660 * @type: value from &iwl_mvm_rxq_notif_type 661 * @sync: ctrl path is waiting for all notifications to be received 662 * @cookie: internal cookie to identify old notifications 663 * @data: payload 664 */ 665 struct iwl_mvm_internal_rxq_notif { 666 u16 type; 667 u16 sync; 668 u32 cookie; 669 u8 data[]; 670 } __packed; 671 672 /** 673 * enum iwl_mvm_pm_event - type of station PM event 674 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 675 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 676 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 677 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 678 */ 679 enum iwl_mvm_pm_event { 680 IWL_MVM_PM_EVENT_AWAKE, 681 IWL_MVM_PM_EVENT_ASLEEP, 682 IWL_MVM_PM_EVENT_UAPSD, 683 IWL_MVM_PM_EVENT_PS_POLL, 684 }; /* PEER_PM_NTFY_API_E_VER_1 */ 685 686 /** 687 * struct iwl_mvm_pm_state_notification - station PM state notification 688 * @sta_id: station ID of the station changing state 689 * @type: the new powersave state, see &enum iwl_mvm_pm_event 690 */ 691 struct iwl_mvm_pm_state_notification { 692 u8 sta_id; 693 u8 type; 694 /* private: */ 695 __le16 reserved; 696 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 697 698 #define BA_WINDOW_STREAMS_MAX 16 699 #define BA_WINDOW_STATUS_TID_MSK 0x000F 700 #define BA_WINDOW_STATUS_STA_ID_POS 4 701 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 702 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 703 704 /** 705 * struct iwl_ba_window_status_notif - reordering window's status notification 706 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 707 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 708 * @start_seq_num: the start sequence number of the bitmap 709 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 710 */ 711 struct iwl_ba_window_status_notif { 712 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 713 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 714 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 715 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 716 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 717 718 /** 719 * struct iwl_rfh_queue_config - RX queue configuration 720 * @q_num: Q num 721 * @enable: enable queue 722 * @reserved: alignment 723 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 724 * @fr_bd_cb: DMA address of freeRB table 725 * @ur_bd_cb: DMA address of used RB table 726 * @fr_bd_wid: Initial index of the free table 727 */ 728 struct iwl_rfh_queue_data { 729 u8 q_num; 730 u8 enable; 731 __le16 reserved; 732 __le64 urbd_stts_wrptr; 733 __le64 fr_bd_cb; 734 __le64 ur_bd_cb; 735 __le32 fr_bd_wid; 736 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 737 738 /** 739 * struct iwl_rfh_queue_config - RX queue configuration 740 * @num_queues: number of queues configured 741 * @reserved: alignment 742 * @data: DMA addresses per-queue 743 */ 744 struct iwl_rfh_queue_config { 745 u8 num_queues; 746 u8 reserved[3]; 747 struct iwl_rfh_queue_data data[]; 748 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 749 750 #endif /* __iwl_fw_api_rx_h__ */ 751
