Searched refs:IS_G4X (Results 1 – 18 of 18) sorted by relevance
213 if (!IS_G4X(dev_priv)) in i9xx_pipe_crc_ctl_reg()219 if (!IS_G4X(dev_priv)) in i9xx_pipe_crc_ctl_reg()225 if (!IS_G4X(dev_priv)) in i9xx_pipe_crc_ctl_reg()249 WARN_ON(!IS_G4X(dev_priv)); in i9xx_pipe_crc_ctl_reg()501 if (IS_G4X(dev_priv)) in intel_crtc_set_crc_source()
39 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_save_display()53 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_restore_display()
587 if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) in stride_is_valid()609 if (IS_G4X(dev_priv)) in pixel_format_is_valid()632 } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { in intel_fbc_hw_tracking_covers_screen()735 if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) && in intel_fbc_can_activate()
99 !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv)) { in i915_adjust_stolen()413 if (!IS_G4X(dev_priv)) in i915_gem_init_stolen()
1033 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { in i915_get_crtc_scanoutpos()1093 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { in i915_get_crtc_scanoutpos()1817 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()2035 if (IS_G4X(dev_priv) || in i9xx_hpd_irq_ack()2073 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in i9xx_hpd_irq_handler()4620 if (IS_G4X(dev_priv)) { in i965_irq_postinstall()4647 if (IS_G4X(dev_priv)) in i965_irq_postinstall()4678 if (IS_G4X(dev_priv)) in i915_hpd_irq_setup()4794 } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { in intel_irq_init()
3223 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || in i9xx_plane_ctl()3716 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); in gpu_reset_clobbers_display()6660 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && in intel_crtc_compute_config()7194 if (IS_G4X(dev_priv) && reduced_clock) in i9xx_compute_dpll()7433 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in i9xx_set_pipeconf()7847 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in i9xx_get_pipe_config()9827 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) in i9xx_cursor_ctl()10029 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_cursor_get_hw_state()10578 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) in intel_plane_atomic_calc_changes()10585 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) in intel_plane_atomic_calc_changes()[all …]
1673 else if (IS_G4X(dev_priv)) in i915_fbc_status()1763 else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || in i915_sr_status()3764 else if (IS_G4X(dev_priv)) in wm_latency_show()3781 IS_G4X(dev_priv)) in wm_latency_show()3842 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) in pri_wm_latency_open()3884 else if (IS_G4X(dev_priv)) in wm_latency_write()
774 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { in intel_device_info_runtime_init()
713 if (IS_G4X(dev_priv)) { in intel_init_audio_hooks()
871 if (ret || !IS_G4X(dev_priv)) in intel_crt_get_modes()
1558 if (IS_G4X(dev_priv)) { in intel_dp_set_clock()1844 if (IS_G4X(dev_priv) || port == PORT_A) in intel_dp_compute_config()1999 if (IS_G4X(dev_priv) && pipe_config->limited_color_range) in intel_dp_prepare()2745 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) in intel_dp_get_config()5355 if (!IS_G4X(dev_priv) && port != PORT_A) in intel_dp_add_properties()
2318 } else if (IS_G4X(dev_priv)) { in intel_infoframe_init()2475 if (IS_G4X(dev_priv)) in intel_hdmi_init()
126 if (IS_G4X(rq->i915) || IS_GEN5(rq->i915)) in gen4_render_ring_flush()
2136 else if (IS_G4X(dev_priv)) in intel_get_gpu_reset()
2765 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) in intel_update_rawclk()
1393 if (IS_G4X(dev_priv)) in i965_hz_to_pwm()
359 } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) { in _intel_set_memory_cxsr()447 else if (IS_G4X(dev_priv)) in intel_set_memory_cxsr()9259 else if (IS_G4X(dev_priv)) in intel_init_clock_gating_hooks()9319 } else if (IS_G4X(dev_priv)) { in intel_init_pm()
2351 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) macro