Home
last modified time | relevance | path

Searched refs:IP0_31_28 (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/drivers/pinctrl/sh-pfc/
Dpfc-r8a77980.c49 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
192 #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0)… macro
316 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
484 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
485 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
486 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
487 PINMUX_IPSR_GPSR(IP0_31_28, A7),
488 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
2639 IP0_31_28
Dpfc-r8a77970.c51 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
162 #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0… macro
268 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
414 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
415 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
416 PINMUX_IPSR_GPSR(IP0_31_28, A7),
417 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
2262 IP0_31_28
Dpfc-r8a77995.c79 #define GPSR1_0 F_(DU_DB0, IP0_31_28)
208 #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_… macro
358 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
550 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
551 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
552 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
2262 IP0_31_28
Dpfc-r8a77990.c98 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
189 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0)… macro
361 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
543 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
544 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
545 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
546 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
2265 IP0_31_28
Dpfc-r8a77965.c105 #define GPSR2_1 F_(IRQ1, IP0_31_28)
223 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
414 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
638 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
639 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
640 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
641 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
[all …]
Dpfc-r8a7795-es1.c100 #define GPSR2_1 F_(IRQ1, IP0_31_28)
218 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
400 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
629 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
630 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
631 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
632 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
634 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
4976 IP0_31_28
Dpfc-r8a7796.c107 #define GPSR2_1 F_(IRQ1, IP0_31_28)
225 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
416 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
639 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
640 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
641 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
642 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
645 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
[all …]
Dpfc-r8a7795.c102 #define GPSR2_1 F_(IRQ1, IP0_31_28)
220 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
411 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
637 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
638 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
639 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
640 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
[all …]
Dpfc-r8a77470.c531 PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
532 PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
533 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),