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Searched refs:INTEL_INFO (Results 1 – 25 of 29) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_color.c395 uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; in bdw_load_degamma_lut()
425 uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; in bdw_load_gamma_lut()
482 INTEL_INFO(dev_priv)->color.degamma_lut_size); in broadwell_load_luts()
568 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; in cherryview_load_luts()
583 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; in cherryview_load_luts()
622 degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size; in intel_color_check()
623 gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size; in intel_color_check()
669 if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && in intel_color_init()
670 INTEL_INFO(dev_priv)->color.gamma_lut_size != 0) in intel_color_init()
672 INTEL_INFO(dev_priv)->color.degamma_lut_size, in intel_color_init()
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Dintel_display.h88 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
255 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
258 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
267 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
272 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
Di915_drv.c290 if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) { in intel_detect_pch()
360 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu); in i915_getparam_ioctl()
365 value = INTEL_INFO(dev_priv)->sseu.eu_total; in i915_getparam_ioctl()
382 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool; in i915_getparam_ioctl()
432 value = INTEL_INFO(dev_priv)->sseu.slice_mask; in i915_getparam_ioctl()
437 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0]; in i915_getparam_ioctl()
442 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz; in i915_getparam_ioctl()
689 if (INTEL_INFO(dev_priv)->num_pipes == 0) in i915_load_modeset_init()
1249 if (INTEL_INFO(dev_priv)->num_pipes) { in i915_driver_register()
1273 if (INTEL_INFO(dev_priv)->num_pipes) in i915_driver_register()
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Di915_query.c16 const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu; in query_topology_info()
Dintel_workarounds.c321 if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i])) in skl_tune_iz_hashing()
330 ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1; in skl_tune_iz_hashing()
735 const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu); in wa_init_mcr()
Dintel_lrc.c2512 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { in make_rpcs()
2514 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << in make_rpcs()
2519 if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { in make_rpcs()
2521 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]) << in make_rpcs()
2526 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { in make_rpcs()
2527 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << in make_rpcs()
2529 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << in make_rpcs()
Dintel_lpe_audio.c114 pdata->num_pipes = INTEL_INFO(dev_priv)->num_pipes; in lpe_audio_platdev_create()
Di915_debugfs.c43 const struct intel_device_info *info = INTEL_INFO(dev_priv); in i915_capabilities()
513 stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes, in i915_gem_object_info()
3272 intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p); in i915_rcs_topology()
4100 val &= INTEL_INFO(i915)->ring_mask; in i915_ring_test_irq_set()
4276 const struct intel_device_info *info = INTEL_INFO(dev_priv); in gen10_sseu_device_status()
4332 const struct intel_device_info *info = INTEL_INFO(dev_priv); in gen9_sseu_device_status()
4360 INTEL_INFO(dev_priv)->sseu.subslice_mask[s]; in gen9_sseu_device_status()
4394 INTEL_INFO(dev_priv)->sseu.eu_per_subslice; in broadwell_sseu_device_status()
4397 INTEL_INFO(dev_priv)->sseu.subslice_mask[s]; in broadwell_sseu_device_status()
4405 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; in broadwell_sseu_device_status()
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Dintel_fbdev.c485 num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) { in intel_fb_initial_config()
673 if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0)) in intel_fbdev_init()
Dintel_ringbuffer.h95 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
99 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
Dintel_guc_submission.c1095 INTEL_INFO(dev_priv)->ring_mask, in guc_clients_create()
1106 INTEL_INFO(dev_priv)->ring_mask, in guc_clients_create()
Dintel_engine_cs.c329 const unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask; in intel_engines_init_mmio()
816 const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu); in intel_calculate_mcr_s_ss_select()
Dintel_i2c.c822 if (INTEL_INFO(dev_priv)->num_pipes == 0) in intel_setup_gmbus()
Di915_drv.h2160 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
2303 #define INTEL_INFO(dev_priv) intel_info((dev_priv)) macro
2495 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
Dintel_ringbuffer.c1533 INTEL_INFO(i915)->num_rings - 1 : in mi_set_context()
2180 num_rings = INTEL_INFO(dev_priv)->num_rings - 1; in intel_ring_default_vfuncs()
Di915_perf.c2746 1000ULL * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz); in oa_exponent_to_ns()
3573 (INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz / 2); in i915_perf_init()
Dintel_display.c5624 val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes); in icl_pipe_mbus_enable()
6396 if (INTEL_INFO(dev_priv)->num_pipes == 2) in ironlake_check_fdi_lanes()
8551 if (INTEL_INFO(dev_priv)->num_pipes == 3 && in ironlake_compute_dpll()
9588 if (INTEL_INFO(dev_priv)->cursor_needs_physical) in intel_cursor_base()
12971 INTEL_INFO(dev_priv)->cursor_needs_physical) { in intel_plane_pin_fb()
15165 if (INTEL_INFO(dev_priv)->num_pipes == 0) in intel_modeset_init()
15212 INTEL_INFO(dev_priv)->num_pipes, in intel_modeset_init()
15213 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); in intel_modeset_init()
16072 if (INTEL_INFO(dev_priv)->num_pipes == 0) in intel_display_capture_error_state()
16114 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; in intel_display_capture_error_state()
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Dintel_pm.c1901 const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1; in vlv_compute_pipe_wm()
2634 fifo_size /= INTEL_INFO(dev_priv)->num_pipes; in ilk_plane_wm_max()
3782 u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size; in intel_get_ddb_size()
7191 switch (INTEL_INFO(dev_priv)->sseu.eu_total) { in cherryview_rps_max_freq()
7809 if (INTEL_INFO(dev_priv)->is_mobile) in pvid_to_extvid()
9346 if (INTEL_INFO(dev_priv)->num_pipes == 1) { in intel_init_pm()
Dintel_bios.c1724 if (INTEL_INFO(dev_priv)->num_pipes == 0) { in intel_bios_init()
Dintel_uncore.c1676 if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask && in i915_reg_read_ioctl()
Di915_gem_execbuffer.c902 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; in reloc_cache_init()
Di915_gpu_error.c1747 INTEL_INFO(i915), in capture_gen_state()
/Linux-v4.19/drivers/gpu/drm/i915/selftests/
Dintel_guc.c80 client->engines != INTEL_INFO(dev_priv)->ring_mask || in validate_client()
270 INTEL_INFO(dev_priv)->ring_mask, in igt_guc_doorbells()
Dhuge_pages.c342 unsigned int supported = INTEL_INFO(i915)->page_sizes; in igt_check_page_sizes()
383 unsigned int saved_mask = INTEL_INFO(i915)->page_sizes; in igt_mock_exhaust_device_supported_pages()
462 unsigned long supported = INTEL_INFO(i915)->page_sizes; in igt_mock_ppgtt_misaligned_dma()
1190 unsigned long supported = INTEL_INFO(i915)->page_sizes; in igt_ppgtt_exhaust_huge()
1420 unsigned long supported = INTEL_INFO(dev_priv)->page_sizes; in igt_ppgtt_pin_update()
Di915_gem_context.c413 ncontexts, INTEL_INFO(i915)->num_rings, ndwords); in igt_ctx_exec()
513 ndwords, INTEL_INFO(i915)->num_rings); in igt_ctx_readonly()

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