Searched refs:IMX7D_PLL_ENET_MAIN_250M_CLK (Results 1 – 3 of 3) sorted by relevance
143 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
54 #define IMX7D_PLL_ENET_MAIN_250M_CLK 41 macro
493 …clks[IMX7D_PLL_ENET_MAIN_250M_CLK] = imx_clk_gate("pll_enet_250m_clk", "pll_enet_250m", base + 0xe… in imx7d_clocks_init()
