Searched refs:IMX6UL_CLK_PLL4_POST_DIV (Results 1 – 2 of 2) sorted by relevance
62 #define IMX6UL_CLK_PLL4_POST_DIV 49 macro
218 clks[IMX6UL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", in imx6ul_clocks_init()
