Searched refs:IMX6SX_CLK_PLL5_POST_DIV (Results 1 – 2 of 2) sorted by relevance
46 #define IMX6SX_CLK_PLL5_POST_DIV 33 macro
255 clks[IMX6SX_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", in imx6sx_clocks_init()
