Searched refs:IMX6SX_CLK_PLL4_AUDIO_DIV (Results 1 – 2 of 2) sorted by relevance
253 clks[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", in imx6sx_clocks_init()527 clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000); in imx6sx_clocks_init()529 clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); in imx6sx_clocks_init()535 clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); in imx6sx_clocks_init()536 clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); in imx6sx_clocks_init()537 clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); in imx6sx_clocks_init()542 clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); in imx6sx_clocks_init()
45 #define IMX6SX_CLK_PLL4_AUDIO_DIV 32 macro
