Searched refs:IMX6SLL_CLK_PLL5_POST_DIV (Results 1 – 2 of 2) sorted by relevance
56 #define IMX6SLL_CLK_PLL5_POST_DIV 45 macro
171 clks[IMX6SLL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", in imx6sll_clocks_init()
