Searched refs:IMX6SLL_CLK_PLL4_POST_DIV (Results 1 – 2 of 2) sorted by relevance
54 #define IMX6SLL_CLK_PLL4_POST_DIV 43 macro
167 clks[IMX6SLL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", in imx6sll_clocks_init()
