Searched refs:IMX6QDL_CLK_PLL4_POST_DIV (Results 1 – 3 of 3) sorted by relevance
206 #define IMX6QDL_CLK_PLL4_POST_DIV 193 macro
206 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
541 …clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", C… in imx6q_clocks_init()
